Cadence Design Systems, Inc.

Vlsi Technology, Inc.

Gerard Tarroux

Jean-Noel Pic

Arnold Ginetti

Fabien Campana

Fabrice Raymond Morlat

Devendra Ramakant Deshpande

Jim Newton

Theodore Alan Paone

Arnold Jean Marie Gustave Ginetti

Yuan-Kai Pei

Reenee Raizada Tayal

Vandana Gupta

Xavier Alasseur

Arnold Jean-Marie Gustave Ginetti

Jean-Marc Bourguet

Jean-Charles Giomi

Olivier Badel

Gautam Kumar

Laurent Robert Chouraki

Jean-Michel Fernandez

Mayank Sharma

Chun-Wen Chiang

Philippe Bourdon

Nicolas Hadacek

Sheng-Wei Lin

Stephane Colancon

Mark Nitters

Manav Khanna

Carole Perrot

Olivier Arnaud

Ramine Roane

Frank Poirot

Embodiments described herein provide a new layout editor tool allowing designers to concurrently edit various aspects of an electronic circuit layout, even at disparate hierarchical levels of the design. The new layout editor tool enables multiple electronic circuit designers to concurrently edit a layout a different hierarchical levels, by logically establishing editable child sub cell-level partitions within a parent layout-level partition, each of which representing various components of the same electronic circuit layout.

Methods and systems of enabling concurrent editing of hierarchical electronic circuit layouts

Disclosed are methods, systems, and articles of manufacture for determining layout equivalence between a plurality of versions of a single layout of a multi-fabric electronic design. These techniques identify a first version and a second version of a layout of an electronic design that spans across multiple design fabrics. One or more collaborative comparator modules are executed to determine whether the first version is identical to or different from the second version of the layout. These techniques further modify the first version or the second version of the layout with discrepancy annotation.

Methods, systems, and computer program product for determining layout equivalence for a multi-fabric electronic design

The present embodiments relate to providing an overlap view of external and internal components of all instance circuit cells related to a master circuit cell in a same layout view. A layout of a circuit having a plurality of instance circuit cells of a master circuit cell is provided. Further, a graphical user interface including a user selectable option for an overlay view is provided. In addition, responsive to the selection of the overlay view, the plurality of instance circuit cells of the master circuit cell is determined. In addition, a plurality of sets of circuit elements, each set of circuit elements including external circuit elements that overlap with a corresponding instance circuit cell of the plurality of instance circuit cells is determined. Further, the plurality of sets of circuit elements overlaid on the master circuit cell is displayed on the layout view.

Editing of layout designs for fixing DRC violations

Methods and systems of an electronic circuit design system described herein provide a new layout editor tool to make edits in an electronic circuit layout. A plurality of partitions is created in the electronic circuit layout. The new layout editor tool enables multiple electronic circuit designers to edit a different partition of the plurality of partitions of the same electronic circuit layout at the same time and save the edited partition locally.

Methods and systems for enabling concurrent editing of electronic circuit layouts

Methods and systems provide aspects of electronics layout design including copying of layout element(s) and graphically defining a one-to-one correspondence between two elements. An exemplary method may include defining a cloning constraint for a layout, rendering a user interface (UI) to display at least one of a schematic and form representation of the layout, and receiving a selection of at least one element in the layout. The method may create a movable drag set based on the selection, and responsive to a matching of at least one element of the drag set with another element in the layout, performing a one-to-one correspondence for the matched elements. The matching may be an overlap of at least one element in the drag set with an element in the layout having the same master.

Circuit design employing stamp patterns

A system and method are provided for accelerated graphic rendering a view of a design layout view represented by a plurality of graphic objects defined by respective geometry data therefor. A database stores the geometry data having location and geometric portions. A large object module actuates retrieval of the geometry data for each of the graphic objects within the view selectively classified to be a large object. A small object module actuates partial retrieval of the geometry data for each of the graphic objects within the view selectively classified to be a small object, the location portion being thereby retrieved exclusive of the geometric portion of the geometry data for each small object. A rendering control module generates a composite image of the design layout view for display, which includes a geometric reproduction of each large object and an abstracted representation of each small object within the view.

System and method for accelerated graphic rendering of design layout having variously sized geometric objects

The present disclosure relates to a computer-implemented method for electronic design automation. The method may include providing, using one or more computing devices, an electronic design including a first net and a second net. The method may include identifying a shortest path between the first net and the second net and determining at least one common shape associated with the shortest path. The method may also include identifying one or more adjacent shapes to the at least one common shape and identifying at least one fork associated with each of the one or more connectivity reference points. The method may further include analyzing an intermediate fork of the at least one fork to identify an electrical short associated with the electronic design.

System and method for identifying an electrical short in an electronic design

The present disclosure relates to a computer-implemented method for electronic design automation. The method may include providing, using one or more computing devices, an electronic design. The method may further include receiving an indication that a cursor is hovering over an overlap associated with the electronic design and in response to receiving the indication, computing one or more via parameters, based upon, at least in part, a topology associated with the overlap. The method may also include displaying, at a graphical user interface, a potential via and allowing, at the graphical user interface, adjustments to the one or more via parameters.

System and method for generating vias in an electronic design by automatically using a hovering cursor indication

Various embodiments implement electronic designs with cloning techniques by identifying a root device corresponding to a master design in an electronic design, performing one or more sets of searches for device correspondence with respect to the root device, and implementing the electronic design by at least characterizing the device correspondence based at least in part upon one or more criterion for the one or more sets of searches. These techniques implement the electronic design by characterizing the device correspondence through at least determining whether the device correspondence represents a clone, a mutant, or a user clone and by identifying and replicating clones, mutants, and/or user clones in the electronic design.

Methods, systems, and articles of manufacture for implementing clone design components in an electronic design

A version management system for fluid guard ring (FGR) PCells uses one or more new version management parameters that are added to the FGR PCell definition to manage the source code versions for a PCell. The system saves instance layout information with a version management parameter that identifies the current PCell source code version for each FGR PCell instance. When evaluated using a newer version of the PCell source code, the instance layout information generated with a previous version of PCell source code can be retrieved. The retrieved layout information will be used during evaluation of the PCell to ensure the integrity of the PCell geometries that were previously verified. The saved layout information will be uniquely identifiable with a hash code of the name-value pairs for one or more parameters associated with the PCell instance.

Version management mechanism for fluid guard ring PCells

Disclosed is an improved mechanism and method for implementing electronic designs. According to some approaches, a method, mechanism, and compute program product is disclosed for implementing electronic designs that allows visual editing of complex objects with advanced editing features, which also provides for automated correspondence of the editing results to parametric values for a programmable object in the design.

Method and system for implementing graphically editable parameterized cells

A method and system for maintaining synchronization between a plurality of layout clones of an integrated circuit design, wherein each layout clone comprises at least one figure. The method comprises tracking relationships between equivalent figures of the plurality of layout clones, wherein the plurality of layout clones are associated with one another within an equivalence group and propagating an edit made in one of the layout clones within an equivalence group to the other layout clones within the equivalence group.

Method and apparatus for maintaining synchronization between layout clones

A method and system reduces the complexity of functions within a Boolean network by breaking the network at certain nodes. Before the flattening phase of a technology independent optimization, the present invention estimates the on-set and off-set complexities of each node of the network. The complexities are estimated by considering the type of function represented by the node, the estimated complexities of any child nodes, and the number of variables in the support of the node. If a node's estimated complexity exceeds a defined complexity limit, then the network is preferably broken at that node. A new node of the same type as the complex node is created, and child nodes of the complex node are appended to the newly created node. In addition, an intermediate node is created as a child of the complex node and the child nodes are removed from the complex node. Removing the child nodes from the complex node reduces the complexity of the node and allows the minimization phase to better optimize the network.

Method and system for breaking complex Boolean networks

A method of automatic synthesis of an integrated circuit, comprising the steps, performed by a programmed machine, of storing a Boolean expression which expresses a combinatorial part of the said integrated circuit, factorizing the Boolean expression and mapping the factorized Boolean expression into a representation of said integrated circuit in hardware terms. The step of factorizing comprises computing a zero-suppressed binary decision diagram unique to and representing the Boolean expression; computing, from said ZBDD, candidate divisors of said expression; selecting candidate divisors; and dividing the Boolean expression by the candidate divisor. The selection of candidate divisors includes computing attributed value on the basis of the saving of literals. The method includes the use of implicit division comprising computing upper and lower bounds for a remainder and then a quotient.

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Villeneuve-Loubet, France

Gerard Tarroux