International Business Machines Corporation

Gerard Orengo

Alain R Blanc

Gerard Richter

Michel Paul Verhaeghe

Michel Poret

Jean-Claude Abbiate

Patrick J Jeanniot

Michel F Ferry

Maurice Cukier

Daniel Mauduit

Jean-Pierre Pantani

Jean-Louis H Marijon

Jean-Claude Froment

By appropriate arrangement of two sets of tables chosen to be complementary, cells which are conveyed through a first multiplexor, n RAM storages and the second are subject to a cell rearrange-ment enabling introduction of at least one bitmap field, thereby producing the n Logical Units. When two bytes which are processed in parallel have to be loaded at the same time in the same RAM storage, one particular byte is stored into one RAM available for a Write operation by use of the first set of tables, thereby causing an alteration to the normal association between the n RAMs and the n Logical Units which is then re-established by the second set of tables.

Switching apparatus comprising a centralized switch core and at least one SCAL element(s) for the attachment of various protocol adapters

A finite state machine connected to a plurality of units which enables to manage the execution of M asynchronous signals to select one of these M asynchronous signals which may become a user clock at a moment which is independent from the pulse of the state machine clock within a minimum of time. The state machine comprises a combinational logic circuit (1) receiving a set of primary input signals (3) which contains N asynchronous input signals and outputting state variable output signals (6) to a state variable register (2). The register (2) is driven by a clock signal (7) which is the clock signal of the state machine and provides M state variable register output signals (51, 52) to M additional latches (10, 20) which delay the signal until they receive a timing pulse (71 or 72) from the combinational circuit. The moment when a pulse is generated is defined by one of the M equations determined by a particular need whose requirements are inputted among the set of primary input signals (3) in the combinational circuit, the equation may also depend on the variable which indicates the signal selected by means of line (50) looping back to combinational logic circuit so that said state machine may be used as a clock select selecting one of the clock input signal to become a user clock; and each time an equation is satisfied, the combinational circuit generates a timing pulse to the corresponding latch which generates then an output signal (53 or 54) to the different units and also to the combinational circuit to indicate the present state of the state machine. Those output signals (53, 54) may be used in connection with a selection means (110) to select which clock input signal is to become a user clock.

Device and method of managing asynchronous events in a finite state

A decimation filter for converting a train of sigma-delta pulses S(i) in synchronism with a sigma-delta clock (fs) into a train of PCM samples which includes counters (321, 331, 341) driven by the sigma-delta clock (fs) and which is continuously incremented by one during N sigma-delta clock pulses, then decremented by two during N following sigma-delta clock pulses and then incremented again by one during N following sigma-delta clock pulses in order to provide a sequence of incrementation parameter DELTA(n). The decimation filter further includes storages (320, 330, 340) for storing the value of the coefficient C(n) corresponding to the decimation filter transfer function, and incrementers (327, 337, 347) driven by the sigma-delta clock fs for incrementing the storages with the incrementation parameter DELTA(n). Finally, the decimation filter includes computers (323, 333, 343, 327, 337, 347) for deriving from the contents C(n) of said storages and from the train of input sigma-delta samples S(i+n) one Pulse Code Modulation (PCM) sample every 3.times.N input sigma-delta samples according to the formula: ##EQU1##

Decimation filter in a sigma-delta analog-to-digtal converter

A sigma-delta converter including a switching component controlled by a first clock having determined transitions for generating a train of sigma-delta code pulses corresponding to an analog input value. The sigma-delta includes circuits for generating a second clock of a same frequency as the first clock and having a negative transition followed after a defined period of time (d2) by a positive transition. The determined transitions of the first clock controlling the switching element occur during said defined period of time. There is also included a circuit controlled by the sigma-delta code pulse train and said second clock for generating a train of sigma-delta pulses insensitive to the mismatch of the rise and fall times of the switching element thereby improving the linearity and the signal-to-noise ratio of the converter. The control of the period of time allows varying of the energy of the pulses in order to provide pulse trains which, when applied to a sigma-delta decoder, provide an analog output value representative of, but attenuated with respect to, the analog input value.

Sigma-delta converter with improved transfer function

Digital filter used in a sigma-delta decoder wherein each input sample is involved in the computation of three consecutive pulse coded modulation (PCM) output samples. During one sigma-delta sampling period, the filter performs three parallel operations by multiplexing one adder running three times faster than the sigma-delta clock for loading one of three accumulators. As the analog-to-digital converter must be kept in phase with remote modem transmit clock, the PCM sampling clock is controlled by the phase tracking performed by adding or subtracting one period of the crystal oscillator from time to time to the PCM sampling clock period. Rotating the order in which the accumulators are loaded by the adder each PCM sampling time enables having zero as the last coefficient value to add to the accumulator, the contents of which is used as PCM output samples. Thus, each PCM sample value is available in the corresponding accumulator one sigma-delta clock period before the last computation. In case of a correction which shortens or lengthens the PCM sampling period, this correction does not change the PCM sample value to be output since the last computation which is either cancelled or repeated, consists in adding zero to the previous accumulator contents.

Digital filter for a modem sigma-delta analog-to-digital converter

A back-up voltage source useful over a comparatively long time interval during a power outage or voltage fluctuation is described. A circuit for adjusting the position of a voltage difference available at the back-up supply outputs is described. A potential difference appearing at the terminals of a floating voltage source is connected to a reference circuit for generating a voltage reference from the difference of potential. A voltage follower connected to the reference and to a second voltage source is employed to cause the voltage follower to reposition the potential difference of the supply so as to force the voltage reference to a level equal to the second voltage source.

Floating back-up power supply

A voltage comparator circuit with a wide common mode input voltage range which extends beyond supply voltage parameter values. The comparator circuit utilizes an input stage having two input transistors, the emitter electrodes of which are connected to receive input signals and the collector electrodes of which are connected to two current sources. A current fixing circuit is coupled to the collector electrodes of said two input transistors and acts to fix the direct current in the collector circuits at a first value IO and the currents supplied by the current sources at a second value k IO, where k is greater than 2. An output stage is provided with two input circuits respectively connected to the collector electrodes of the two input transistors and with a logic circuit arrangement set to either one of two logic levels in accordance with the sign of the difference in the voltages applied to the pair of emitter electrodes of the two input transistors.

Voltage comparator with a wide common mode input voltage range

A digital signal distribution system for distributing digital signals to remote points of a machine. It is comprised of a distribution device arranged at each of said points. In each device, a receiver receives on its true and complementary inputs, the signal to be distributed. The drivers are connected to the receivers through a crossed connection, the true output of the receiver being connected to the complementary input of the driver, and the complementary output of the receiver being connected to the true input of the driver, so as to cancel the skew of the pulse width of the signal to be distributed. The signals on outputs of the driver circuits can be utilized locally or transmitted to another remote point.

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Biot, France

Gerard Orengo