International Business Machines Corporation

Gerard M Salem

Franco Motika

Mary Prilotski Kusko

John D Parker

Preetham M Lobo

Mitesh A Agrawal

Timothy J Von Reyn

Anand Haridass

Tobias Webel

R Dean Adams

Robert James Lynch

Mathew I Ringler

Sreekala Anandavally

Subramanian Srikanteswara Iyer

Chandrasekharan Kothandaraman

Michael F Fee

Steven Michael Douskey

Robert J Sonnelitter, Iii

Adam B Collura

Peter Anthony Sandon

Thomas Pflueger

Carl Alfred Bender

Arthur J O'Neill, Jr

Vinod Ramadurai

Robert Maurice Houle

Andrew A Turner

Gary William Maier

Orazio Pasquale Forlenza

Ulrich Weiss

Jay Gerald Heaslip

Stephen Frank Geissler

Cédric Lichtenau

Rolf B Hilgendorf

Jens Kuenzer

Richard A Swetz

Edward C McCain

Craig R Selinger

Diyanesh B C Vidyapoornachary

Steven E Charlebois

Miles G Canada

Ben Jesse Nathanson

Matthew Edward Aubertine

Timothy J Vonreyn

Dana J Thygesen

Lisa Nayak

Harold J Broker

Michael Herasimtschuk

Michael A Granato

Kianoush Beyzavi

Ronald P Checca

Dongho Lee

David A Haeussler

Michael J Jurkovic

Paul R Zehr

Singpui Zee

A method includes executing a test against a first structure and a second structure of a built-in self-test circuit. Each of the first and second structures include a plurality of latches arranged as a plurality of stump chains. The method also includes unloading a first result of the test from the plurality of stump chains of the first structure and a second result of the test from the plurality of stump chains of the second structure. The method further includes determining that the plurality of stump chains of the first structure includes a faulty latch based on the first result not matching the second result.

Diagnostic enhancement for multiple instances of identical structures

Methods, systems and computer program products for loading, storing and executing dynamically modifiable functional exercisers are provided. Aspects also include receiving a plurality of functional exercisers by a secondary reload memory disposed on a device-under-test. Aspects include loading at least a first functional exerciser from the secondary reload memory into a primary execution memory disposed on the device-under-test. Aspects include executing and modifying the first functional exerciser stored in the primary execution memory. Aspects further include, responsive to determining based on a test algorithm that one or more functional exercisers of the plurality have not been fully executed, loading a second functional exerciser from the secondary reload memory into the primary execution memory.

Iterative functional test exerciser reload and execution

Providing non-destructive recirculation test support in a device under test includes determining an initial latch allocation of a plurality of latches to form a plurality of self-test chains for the device under test. An optimized latch allocation to the self-test chains is determined based on a plurality of physical and logical grouping constraints. One or more of the latches are adjusted and reassigned between one or more of the self-test chains based on the optimized latch allocation. A recirculating feedback is coupled from an output of at least one of the self-test chains to a recirculation selector. A test input source is coupled to the recirculation selector, where the recirculation selector is operable to select between providing the test input source or the recirculating feedback to an input of the at least one of the self-test chains.

Non-destructive recirculation test support for integrated circuits

Embodiments include methods, and computer system, and computer program products for performing test and calibration of integrated sensors on a processor chip. Aspects include: initializing, by a tester program, an on-chip service engine of processor chip, performing and completing, by on-chip service engine, test and calibration of integrated sensors. The method may also include: loading and decoding tester program into an on-chip service engine memory, testing and calibrating each integrated sensor, which may include: selecting an integrated sensor for test and calibration, loading sensor test and calibration patterns and parameters, and sensor test code, and executing the sensor test code to test and calibrate integrated sensors, writing results of the test and calibration to a predetermined location of the on-chip service engine memory, and writing a return code of test and calibration to another predetermined location of on-chip service engine memory, when every integrated sensor is tested and calibrated.

Methods and systems for performing test and calibration of integrated sensors

An embodiment of the present invention provides a computer-implemented method for functional test and diagnostics of integrated circuits. The computer-implemented method includes executing one or more functional test exercisers in a functional execution sequence for a device under test up to one or more checkpoints, applying dynamic clock switching to a clock of the device under test to identify one or more likely causes of a failure identified at the one or more checkpoints, and includes iteratively invoking a portion of the functional execution sequence between a plurality of the checkpoints to progressively isolate the one or more likely causes of the failure as a most likely failure source based at least in part on the applied dynamic clock switching.

Functional diagnostics based on dynamic selection of alternate clocking

Embodiments include methods, and computer system, and computer program products for performing system functional test on a chip having partial-good portions. Aspects include: initializing, by system functional test software, a service engine of the chip, performing, by service engine, system functional test, and completing system functional test of chip. The chip may include service engine, a service engine memory and one or more 'partial-good' portions. The initializing may include: loading system functional test software into the service engine memory, identifying each 'partial-good' portion of the chip, writing a &#x201c;partial-good&#x201d; parameter for each &#x201c;partial-good&#x201d; portion of the chip identified to service engine memory, and triggering execution of system functional test. Method may include: decoding system functional test software, retrieving &#x201c;partial-good&#x201d; parameters, initializing &#x201c;partial-good&#x201d; portions of chip, and performing system functional test on &#x201c;partial-good&#x201d; portions of chip. The chip may include is a processor chip that has one or more &#x201c;partial-good&#x201d; cores.

Performing system functional test on a chip having partial-good portions

Structurally assisted functional test and diagnostics include executing one or more functional test exercisers in a functional execution sequence for a device under test up to one or more checkpoints. One or more built-in structural test support circuits of the device under test is applied to identify one or more likely causes of a failure identified at the one or more checkpoints. A portion of the functional execution sequence between a plurality of the checkpoints is iteratively invoked to progressively isolate the one or more likely causes of the failure as a most likely failure source in combination with one or more results from the one or more built-in structural test support circuits.

Structurally assisted functional test and diagnostics for integrated circuits

A computer system verifies functional test patterns for diagnostics, characterization and manufacture testing. The system generates, by a system designer, verification sequences including initial trace traces selected from a verification sequence data to test system functional design. The system includes a trace module, an emulated pattern generator module, and a test pattern verification and debug module. The trace module adds custom information to the traces to generate modified traces and the system executes the verification sequences against a device to generate traces. The trace module further processes the modified traces by parsing the captured modified traces. The system verifies data integrity and summarizes statistics of the captured traces. The emulated pattern generator module generates emulated test patterns, which are based on the output of the trace module and have independent format streams compatible with a device test port. The test pattern verification and debug module verifies the emulated test patterns.

Methods and systems for generating functional test patterns for manufacture test

Embodiments include methods, computer systems and computer program products for generating functional test patterns for diagnostics, characterization and manufacture test. Aspects include: receiving from a system designer, via a design verification tool module, certain verification sequences configured to verify system functional design, executing the verification sequences received at a functional exerciser module against a device to generate various traces, capturing traces generated in emulation compatible format, processing traces captured via trace processor module, including parsing the traces captured, verifying data integrity of the traces captured, and summarizing statistics of the traces captured, generating, via an emulated pattern generator module, a predetermined number of emulated test patterns having tester independent format 'streams' of data compatible with a device test port based on output of the trace processor module, and processing, via a tester specific post-processor module, the emulated test patterns to generate functional test patterns using a tester specific post-processor module.

A method, system, and/or computer program product of scanning of an integrated circuit including chiplets to isolate fault locations is provided herein. The scanning of the integrated circuit includes providing, by a pervasive of the integrated circuit, an input to the chiplets. Each of the chiplets can include a pervasive satellite, a multiplexer, and latches. The scanning of the integrated circuit includes also scanning, by each pervasive satellite of the chiplets, data based on the input via the multiplexer into the latches to produce scan data for each of the chiplets. The scanning of the integrated circuit also includes comparing, by the pervasive of the integrated circuit, the scan data of each of the chiplets to expectant data stored on the pervasive to isolate the fault locations.

Optimized chain diagnostic fail isolation

Embodiments of the disclosure are directed to an apparatus that comprises a first core susceptible to an error condition, and a second core configured to perform a diagnostic on the first core to identify a cause of the error condition and an action to remedy the error condition in order to recover the first core.

Core diagnostics and repair

Multi-core diagnostics and repair using firmware and spare cores

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Essex Junction, VT, United States of America

Gerard M Salem