International Business Machines Corporation

Gerard Dalboussiere

Kenneth James Barker

Pierre Austruy

Michel L Costes

Rene R Castel

Wilburn D Draper

Michel Kulakowski

The high speed line adapter comprises a bit handling layer (34,46) and a byte handling layer (36,50) and a receive queue mechanism (48). The bit layer receives the frames from the high speed line 9. It performs the SDLC protocol, it removes the flag and BCC characters and adds one ending condition control character which indicates whether the frame was correctly received or not. It causes the address and control fields, the data if any and the ending condition character to be stored into a receive queue buffer at the first free address. The byte layer 50 takes out the frame characters from the receive queue as soon as a pool buffer is available in the memory of the central unit of the communication controller. It sends the data if any to said memory through a direct access memory bus and sends the address and control fields and the ending condition to the microprocessor of the adapter. The provision of the receive queue mechanism allows high speed lines to be connected to a communication controller, without modifying its network control program.

Very high speed line adapter for a communication controller

In a data processing equipment handling communication lines connected to a central control unit through adapters and a CCU input/output bus, an error reporting device is provided in each adapter for reporting error conditions occurring in the adapter to the central control unit. The adapters are of the type including a microcode controlled microprocessor provided with input and output buses connected to the CCU input/output bus through an interface. The error reporting device in association with dedicated circuits in the interface insures the transmission of the error conditions occurring in the adapter to the central control unit, even when such error conditions affect the integrity of the microcode. When the error reporting device detects an error affecting the microcode integrity, it generates a hard stop signal which causes the operation of the microprocessor under the control of the microcode to be stopped and the error conditions to be transferred to the central control unit making use of the same paths as those used for reporting errors which do not affect the microcode integrity.

Device for reporting error conditions occurring in adapters, to the data

Adapter interfaces (ADAPT) and line driver interfaces (RDVP and RDVC) are divided into subgroups within a pyramid type of architecture. Each subgroup is provided with independent preselection means for determining the path through the pyramid from the CCU BUS to the adapter to be serviced first.

System for selecting interfaces on a priority basis

A dynamic preselect interrupt priority circuit in which a plurality of adapters dynamically readjust priority until selected whereupon adjustment stops and the adapter having the highest interrupt and position priority is selected.

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La Colle, Loup, France

Gerard Dalboussiere