Texas Instruments Corporation

Texas Instruments France

Gerard Chauvel

Serge Bernard Lasserre

Dominique D'Inverno

Gilbert Cabillic

Jean-Philippe Lesot

Maija Kristiina Kuusela

Jean-Paul Routeau

Dominique Benoit Jacques d'Inverno

Frédéric Parain

Michel Banâtre

Salam Majoul

Pierre Calippe

Francis Aussedat

Frederic Boutaud

Brian Okchon Chae

Gerard V Benbassat

Mario Giani

Tiemen T Spits

Frank L Laczko, Sr

Karen L Walker

Matthew A Woolsey

Marion C Lineberry

Y Paul Chiang

Mikael Peltier

Michael McMahon

Mark E Paley

Sebastiano D'Arrigo

Darvin R Edwards

Jimmie D Childers

Hiroshi Miyaguchi

Marc Couvrat

Michel P Banatre

Eric L Badi

Edward E Ferguson

Gael Clave

Teresa Higuera

Valerie Issarny

Jean-Luc Villevieille

Jean Ciroux

Dominique D'inverno

Serge Lassère

A method and system of accessing display window memory. At least some of the illustrative embodiments are methods comprising abstracting display window memory by way of a first software object, accessing the display window memory by routines of a graphics library executed on a first processor (the accessing by way of the first software object), and displaying a window on a display screen, contents of the window selected at least in part by the routines of the graphics library.

Method and system of accessing display window memory

Methods and apparatuses are disclosed for managing memory write back. In some embodiments, the method may include examining current and future instructions operating on a stack that exists in memory, determining stack trend information from the instructions, and utilizing the trend information to reduce data traffic between various levels of the memory. As stacked data are written to a cache line in a first level of memory, if future instructions indicate that additional cache lines are required for subsequent write operations within the stack, then the cache line may be written back to a second level of memory. If however, the future instructions indicate that no additional cache lines are required for subsequent write operations within the stack, then the first level of memory may avoid writing back the cache line and also may keep it marked as dirty.

Dirty cache line write back policy based on stack size trend information

A method and system for performing a Java interrupt. At least some of the illustrative embodiments are methods comprising executing a thread having a context on a stack based on a first program counter, detecting an interrupt while executing the thread (wherein execution of the thread is temporarily suspended), and executing a method portion to handle the interrupt (wherein the method portion is executed on the stack based on the first program counter, and wherein the context during execution of the method portion is the same as during execution of the thread).

Performing java interrupt with two program counters

An electronic device comprising decode logic that decodes instructions and a stack coupled to the decode logic. A group of instructions causes the decode logic to push onto the stack, after halting processing of a first thread at a switch point and prior to processing a second thread, a minimum amount of information needed to resume execution of the first thread at the switch point and not information not needed to resume execution of the first thread at the switch point.

Storing contexts for thread switching

A wireless data platform comprises a plurality of processors. Channels of communication are set up between processors such that they may communicate information as tasks are performed. A dynamic cross compiler executed on one processor compiles code into native processing code for another processor. A dynamic cross linker links the compiled code for other processor. Native code may also be downloaded to the platform through use of a JAVA Bean (or other language type) which encapsulates the native code. The JAVA Bean can be encrypted and digitally signed for security purposes.

Mobile electronic device having a host processor system capable of dynamically canging tasks performed by a coprocessor in the device

A system comprises a first processor, a second processor coupled to the first processor, memory coupled to, and shared by, the first and second processors, and a synchronization unit coupled to the first and second processors. The second processor preferably comprises stack storage that resides in the core of the second processor. Further, the second processor executes stack-based instructions while the first processor executes one or more tasks including, for example, managing the memory via an operating system that executes only on the first processor. Associated methods are also disclosed.

Multi-processor computing system having a JAVA stack machine and a RISC-based processor

A method and system for implementing a micro-sequence based security model in a processor. More particularly, micro-sequences and JSM hardware resources are employed to construct a security model invisible to applications, and when memory constraints are in place, extend a complex security model in JSM code by implementing a micro-sequence security trigger. The method includes micro-sequence based security policy that determines whether an instruction accesses a privileged resource associated with a processor and when not already in privilege mode and not executing a micro-sequence, the micro-sequence based security policy is applied to the instruction to control access to the privileged resource according to the security policy.

Micro-sequence based security model

A processor executes an instruction that causes a comparison to be performed between contents of a first register and contents of a second register and between the contents of the first register and a predetermined value. The instruction is particularly useful for determining whether an attempted access (either a load or write) to an array improperly targets a location outside the boundary of the array. In some embodiments, a system (e.g., a communication device such as cellular telephone) includes a processor capable of executing the instruction as described above.

Compare instruction

An electronic device that comprises a processor including an individual instruction and a first group of instructions. The device further comprises a memory externally coupled to the processor, as well as a second group of instructions. When executed, the first group of instructions causes the processor to execute the second group of instructions in lieu of the individual instruction.

Removing local RAM size limitations when executing software code

A method and system to emulate an M-bit instruction set. At least some of the illustrative embodiments are a method comprising fetching at least a portion of an instruction (the instruction from a first instruction set that is not directly executable by a processor), indexing into a table to an index location (the index location based on the at least a portion of the instruction), executing a first series of instructions directly executable by the processor (the first series of instructions pointed to by the table at the index location), and thereby emulating execution of the instruction from the first instruction set.

Method and system to emulate an M-bit instruction set

A mobile device () manages tasks () using a scheduler () for scheduling tasks on multiple processors (). To conserve energy, the set of tasks to be scheduled are divided into two (or more) subsets, which are scheduled according to different procedures. In a specific embodiment, the first subset contains tasks with the highest energy consumption deviation based on the processor that executes the task. This subset is scheduled according to a power-aware procedure for scheduling tasks primarily based on energy consumption criteria. If there is no failure, the second subset is scheduled according to a real-time constrained procedure that schedules tasks primarily based on the deadlines associated with the various tasks in the second subset. If there is a failure in either procedure, one or more tasks with the lowest energy consumption deviation are moved from the first subset to the second subset and the scheduling is repeated.

Energy-aware scheduling of application execution

A processor comprising fetch logic adapted to fetch instructions from memory and decode logic coupled to the fetch logic and adapted to decode the fetched instructions. If a bit in the decode logic is in a first state, a particular fetched instruction is skipped and a group of one or more instructions is executed in lieu of the particular fetched instruction. If the bit is in a second state, both the group and the particular fetched instruction are executed.

Modifying an instruction stream using one or more bits to replace an instruction or to replace an instruction and to subsequently execute the replaced instruction

A method for generating program code for translating high level code into instructions for one of a plurality of target processors comprises first determining a desired program code characteristic corresponding to a target processor. Then, selecting one or more predefined program code modules from a plurality of available program code modules in accordance with said desired program code characteristic, and generating program code for translating high level code into instructions for said target processor from said selected one or more predefined program code modules. Preferably, the method comprises forming agglomerated program code from a plurality of program code modules in accordance with said desired program code characteristic.

Data processing apparatus, system and method

Systems, methods, and storage media for accessing indirect memory in Java applications are provided. In some embodiments, a storage medium is provided that comprises Java application software that performs one or more operations on an indirect memory of a device. The software comprises instructions that create an instance of a Java class representing the indirect memory, and instructions that access a memory element of the indirect memory using an element unique identifier ('euid') of the memory element. Other embodiments provide a method for accessing memory elements of a device that comprises creating an instance of a Java class representing the memory elements, and accessing a memory element of the memory elements using an element unique identifier ('euid') of the memory element, wherein the memory elements are not mapped into the data memory space of the processor.

Method and system for accessing indirect memories

A processor (e.g., a co-processor) executes a stack-based instruction set and another instruction in a way that accelerates the execution of the stack-based instruction set, although code acceleration is not required under the scope of this disclosure. In accordance with at least some embodiments of the invention, the processor may comprise a multi-entry stack usable in at least a stack-based instruction set, logic coupled to and managing the stack, and a plurality of registers coupled to the logic and addressable through a second instruction set that provides register-based and memory-based operations.

Growing community of inventors

Antibes, France

Gerard Chauvel