International Business Machines Corporation

Geraldine C Schwartz

Fernand J Dorleans

Gerald R Larsen

Paul M Schaible

Charles L Standley

Louis L Hsu

John Anthony Fitzsimmons

Jerome Michael Eldridge

Roy Arthur Carruthers

Paul J Tsang

Joseph S Logan

John L Mauer, Iv

Liang-Choo Hsia

Laura B Rothman

James A Jubinsky

Robert W Zielinski

Richard Flitsch

Michael H Lee

Gary S Selwyn

Wen-yaung Lee

Laura Beth Rothman

Linda M Ephrath

Reid S Bennett

Albert P Lee

Laura B Zielinski

Valeria Platter

George S Gati

The present invention is directed to a unique silicon based MOS transistor having an inverse-T refractory metal gate structure. The gate fabricated according to this invention comprises a main CVD tungsten portion and a lower sputtered tungsten portion outwardly extending from the bottom of the CVD portion such that a cross section of the gate appears as an inverted 'T'. A Cl.sub.2 /O.sub.2 plasma etch is used to etch the CVD tungsten layer and a chemical etch is used to etch the sputtered tungsten layer to form the gate electrode. It has been discovered that sputtered tungsten is more resistant to Cl.sub.2 /O.sub.2 reactive ion etch than is CVD tungsten. The sputtered tungsten layer acts as a shield to protect the underlying gate oxide layer from ion damage throughout the fabrication process.

CMOS transistor with two-layer inverse-T tungsten gate

The present invention is directed to a unique method for fabricating a silicon based MOS transistor having an inverse-T refractory metal gate structure. The gate fabricated according to this invention comprises a main CVD tungsten portion and a lower sputtered tungsten portion outwardly extending from the bottom of the CVD portion such that a cross section of the gate appears as an inverted 'T'. A Cl.sub.2 /O.sub.2 plasma etch is used to etch the CVD tungsten layer and a chemical etch is used to etch the sputtered tungsten layer to form the gate electrode. It has been discovered that sputtered tungsten is more resistant to Cl.sub.2 /O.sub.2 reactive ion etch than is CVD tungsten. The sputtered tungsten layer acts as a shield to protect the underlying gate oxide layer from ion damage throughout the fabrication process.

Method for fabricating a MOS transistor with two-layer inverse-T

A SiCr microfuse, deletable either by electrical voltage pulses or by laser pulses, for rerouting the various components in an integrated circuit, as where redundancy in array structures is implemented, and the method of fabricating same, at any wiring level of the chip, by utilizing a direct resist masking of the SiCr fuse layer to eliminate problems of mask damage and residual metal adjacent the fuse.

Structure and fabrication of SiCr microfuses

SiCr microfuses

Laser induced fluorescence is utilized to detect and control the reactive ion etch-through of a given layer in a wafer by detecting a large change in the concentration of a selected minor species from the wafer in the etching plasma. This selected minor species must be present in a significantly different concentration in the etched given layer compared to adjacent layers in the wafer in order to provide a proper endpoint detection. In one embodiment, when the large change in the selected minor species concentration is detected, then the RF electrodes for the reactor are automatically de-energized.

Trench etch endpoint detection by LIF

A composite insulator structure separating adjacent layers of patterned metal on an LSI chip is disclosed. The bottom layer of sputtered oxide is thicker than the top layer and is preferably planarized. The top layer is conformal plasma nitride so as to uncover unwanted projections on the underlying metal and prevent interlevel shorting between the patterned layers.

Composite insulator structure

Use of a dual composite mask for a lift-off multi-layered structure process in which a base component layer acts as an etch stop for reactive ion etching of overlying layers.

Planar multi-level metal process with built-in etch stop

Formation of planar conductor/insulator semiconductor devices utilizing hafnium coated aluminum based metallization with a magnesium oxide mask for dry etching of the metallization and deposition of planar insulation. The hafnium coating is used to protect the aluminum metallization during mask removal, and as a registration enhancer for subsequent electron-beam processing.

Method for forming planar metal/insulator structures

Aluminum-based alloy films and metallization layers that are patterned by reactive ion etching (RIE) are passivated by etching surface portions of the films or layers with a phosphoric-chromic mixture to remove contaminants and then oxidizing the exposed surface portions in an oxygen atmosphere.

Passivation of RIE patterned al-based alloy films by etching to remove

The use of a molybdenum diffusion barrier between a copper layer and a magnesium oxide dry etch mask to obtain and insure adhesion between the two.

Dry etching of copper patterns

Aluminum microcircuits which have been prepared by reactive-ion etching are stabilized against open circuits and short circuits by treating the microcircuits in an oxygen-containing atmosphere at a temperature of from about 200.degree. C. to about 450.degree. C.

Stabilization process for aluminum microcircuits which have been

Magnesium oxide is deposited on a substrate as a mask with a pattern of openings which exposes a corresponding pattern of a surface of a substrate which is to be subjected to dry etching. In a specific application, the magnesium oxide mask is employed to delineate a conductor pattern on semiconductor substrates by dry etching.

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Poughkeepsie, NY, United States of America

Geraldine C Schwartz