International Business Machines Corporation

Agere Systems Inc.

Gerald Warren Gibson, Jr

Josephine B Chang

Mark B Ketchen

Maxime Darnon

Pratik P Joshi

Qinghuang Lin

Roy Rongqing Yu

Mary Beth Rothwell

James J Bucchignano

Seong Jin Koh

Ying Di Zhang

Robert K Montoye

Kathryn Turner Schonenberg

Takeo Yasuda

Hongwen Yan

Kurt George Steiner

Susan Clay Vitkavage

Scott Jessen

Ryan M Martin

Corrado P Mancini

Michael Karunendra Selvanayagam

David Lokken-Toyli

Milton Beachy

Mario Pita

Steve Lytle

Kathryn Jessica Pooley

Shayne Cairns

A method of manufacturing a travelling wave parametric amplifier (TWPA) includes forming a superconducting junction on a substrate. Trenches are etched away through a metal surface and into a layer of dielectric material. The trenches define a plurality of fingers positioned in an interdigitated arrangement of capacitors defined by a metal and a dielectric material that remains from the etched away metal surface and the layer of dielectric material.

Low loss travelling wave parametric devices using planar capacitors

Systems and methods for optimizing a pipeline are described. A system can generate at least one pair of single flux quantum (SFQ) clock signals based on a stream of SFQ pulses. Each pair of SFQ clock signals can include a first SFQ clock signal and a second SFQ clock signal that is out of phase with the first SFQ clock signal. The second SFQ clock signal can have the same frequency as the first SFQ clock signal. The system can define, for each pair of SFQ clock signals, a first clock cycle and a second clock cycle based on the first SFQ clock signal and the second SFQ clock signal. The second clock cycle can be greater than the first clock cycle. The system can assign the first and second clock cycles to different stages of a pipeline based on delays by the different stages.

Asymmetrical clock separation and stage delay optimization in single flux quantum logic

Techniques for forming respective groups of quantum circuit elements (QCEs) on respective crystalline surfaces of a crystalline dielectric (CD) layer are presented. Vias can be formed in the CD layer. Second QCEs can be formed on a second crystalline surface of the CD layer. A seal layer can be applied to the patterned second metallization layer that forms the second QCEs. A handle wafer can be bonded to the seal layer. The chip stack can be turned over to place a substrate at the top, and handle wafer at the bottom, of the chip stack. The substrate and a buried oxide layer can be removed to expose the first crystalline surface of the CD layer. First QCEs can be formed on the first crystalline surface of the CD layer. A portion of the first QCEs can be coupled or interconnected to a portion of the second QCEs.

Scaled quantum circuits

Techniques and methods to form smooth metal layers deposited onto selected surfaces of Josephson junction devices are provided. For example, one or more embodiments described herein can comprise depositing a layer of a first material comprising metal atom species on a selected surface of a device layer; depositing a layer of a second material on a surface of the layer of first material; and performing plasma etching on the layer of second material and the layer of first material to form an etched surface of the layer of first material that is smoother than the surface of the layer of first material, as deposited.

Smooth metal layers in Josephson junction devices

A technique relates to a trilayer Josephson junction structure. A dielectric layer is on a base electrode layer that is on a substrate. A counter electrode layer is on the dielectric layer. First and second counter electrodes are formed from the counter electrode layer. First and second dielectric layers are formed from the dielectric layer. First and second base electrodes are formed from base electrode layer. The first counter electrode, first dielectric layer, and first base electrode form a first stack. The second counter electrode, second dielectric layer, and second base electrode form a second stack. A shunting capacitor is between first and second base electrodes. An ILD layer is deposited on the substrate, the first and second counter electrodes, and the first and second base electrodes. A contact bridge connects the first and second counter electrodes. An air gap is formed underneath the contact bridge by removing ILD.

Trilayer Josephson junction structure with small air bridge and no interlevel dielectric for superconducting qubits

Trilayer josephson junction structure with small air bridge and no interlevel dielectric for superconducting qubits

The present disclosure relates to a structure comprising and to methods of making the structure and using the structure to measure the electrical characteristics of carbon nanotubes.

Methodology for evaluation of electrical characteristics of carbon nanotubes

The present disclosure relates to a structure comprising

The present disclosure relates to a method for selectively etching-back a polymer matrix to expose tips of carbon nanotubes comprising:

Selective etch back process for carbon nanotubes intergration

A microelectronic structure, and in particular a semiconductor structure, includes a substrate and a dielectric layer located over the substrate. In addition at least one alignment mark is located interposed between the dielectric layer and the substrate. The at least one alignment mark comprises, or preferably consists essentially of, at least one substantially present element having an atomic number at least 5 greater than a highest atomic number substantially present element within materials surrounding the alignment mark Also included within the microelectronic structure is a dual damascene aperture located within the dielectric layer. The dual damascene aperture may be fabricated using, among other methods, a hybrid lithography method that uses direct write lithography and optical lithography, in conjunction with the at least one alignment mark and an electron beam as an alignment beam.

Microelectronic structure including dual damascene structure and high contrast alignment mark

A method for forming high density emission elements and field emission displays formed according to the method. Oxygen and a silicon etchant are introduced into a plasma etching chamber containing a silicon substrate. The oxygen reacts with the silicon surface to form regions of silicon dioxide, while the silicon etchant etches the silicon to form the emission elements. The silicon dioxide regions mask the underlying silicon during the silicon etch process. High density and high aspect ratio emission elements are formed without using photolithographic processes. The emission elements formed according to the present invention provide a more uniform emission of electrons. Further, a display incorporating emission elements formed according to the present invention provides increased brightness. The reliability of the display is increased due to the use of a plurality of emission elements to supply electrons for stimulating the phosphor substrate material to produce the image.

High-density field emission elements and a method for forming said emission elements

The present invention relates to improved methods and structures for forming interconnect patterns in low-k or ultra low-k (i.e., having a dielectric constant ranging from about 1.5 to about 3.5) interlevel dielectric (ILD) materials. Specifically, reduced lithographic critical dimensions (CDs) (i.e., in comparison with target CDs) are initially used for forming a patterned resist layer with an increased thickness, which in turn allows use of a simple hard mask stack comprising a lower nitride mask layer and an upper oxide mask layer for subsequent pattern transfer. The hard mask stack is next patterned by a first reactive ion etching (RIE) process using an oxygen-containing chemistry to form hard mask openings with restored CDs that are substantially the same as the target CDs. The ILD materials are then patterned by a second RIE process using a nitrogen-containing chemistry to form the interconnect pattern with the target CDs.

Structures and methods for low-k or ultra low-k interlayer dielectric pattern transfer

A process and apparatus for controlling an etchant gas concentration in an etch chamber. The etchant gas concentration and an inert gas concentration are determined and the latter concentration is used to normalize the etchant gas concentration. The normalized value is compared with a predetermined reference value and the flow of etchant gas into the chamber is controlled in response thereto.

Growing community of inventors

Danbury, CT, United States of America

Gerald Warren Gibson, Jr