International Business Machines Corporation

Gerald Walter Jones

Voya Rista Markovich

Luis Jesus Matienzo

Anastasios Peter Angelopoulos

Thomas R Miller

William E Wilson

Ashwinkumar C Bhatt

Heike Marcello

Kostas I Papathomas

Anilkumar Chinuprasad Bhatt

John Steven Kresge

Francis Joseph Downes, Jr

Konstantinos I Papathomas

James Warren Wilson

Ross William Keesler

Thomas P Duffy

Jeffrey McKeveny

Frank Daniel Egitto

Robert Maynard Japp

David Brian Stone

Donald Seton Farquhar

Bernd Karl Appelt

David James Alcoe

James Robert Wilcox

William John Rudik

Gary A Johansson

Elizabeth F Foster

Charles Robert Davis

Robert David Sebesta

Joseph Alphonse Kotylo

William D Taylor

Douglas Adam Cywar

Richard William Malek

Nageshwer Rao Bantu

Paul Joseph Hart

Cheryl L Tytran-Palomaki

Robert J Owen

Edward P McLeskey

Anaya Kumar Vardya

Yenloan H Nguyen

John M Lauffer

David John Russell

Suryadevara Vijayakumar Babu

David Erle Houser

William J Summa

James R Stack

Kenneth Lynn Potter

Neng-Hsing Lu

W Robert Pratt

Heinke Marcello

James P Paoletti

A semiconductor chip carrier having an increased chip connector and plated through hole density. In particular, a substrate having a plurality of plated through holes therein, and a fatigue resistant redistribution layer thereon. The redistribution layer includes a plurality of vias selectively positioned over and contacting the plated through holes. The substrate further including a ground plane, two pair of signal planes, and two pair of power planes, wherein the second pair of power planes are located directly underneath the external dielectric layer. A buried plated through hole within the substrate.

Integrated circuit structure

A method of making a multi-layered interconnect structure. First and second electrically conductive members are formed on the first and second dielectric layers, respectively. The dielectric layer are formed on opposing surfaces of a thermally conductive layer. A first and second electrically conductive layer is formed within the first dielectric layer. The second electrically conductive layer includes shielded signal conductors and is positioned between the first electrically conductive layer and the thermally conductive layer. A plated through hole (PTH) formed through the interconnect structure is electrically connected to one of the first and second electrically conductive members and to one of the shielded signal conductors. A third dielectric layer, formed on the first dielectric layer and on portions of the first electrically conductive members, substantially overlies the PTH and includes a high density interconnect layer for providing an electrical path from an electronic device to the shielded signal conductors.

Method of making a multi-layered interconnect structure

A process of fabricating a circuitized structure is provided. The process includes the steps of providing an organic substrate having circuitry thereon; applying a dielectric film on the organic substrate; forming microvias in the dielectric film; sputtering a metal seed layer on the dielectric film and the microvias; plating a metallic layer on the metal seed layer; and forming a circuit pattern thereon.

Process of fabricating a circuitized structure

The present invention provides new methods for electroless plating of metal particularly gold and copper onto substrates, such as circuitized substrates, which reduces processing steps, reduces metal consumption, and reduces the scraping of parts due to contamination. The method employs a permanent plating resist. The method for electrolessly plating metal onto a substrate, including the following steps: providing: an uncured, photoimagable, dielectric permanent plating resist comprising: from about 10 to 80% of phenoxy polyol resin which is the condensation product of epichlorohydrin and bisphenol A, having a molecular weight of from about 40,000 to 130,000; from about 20 to 90% of an epoxidized multifunctional bisphenol A formaldehyde novolac resin having a molecular weight of from about 4,000 to 10,000; from 0 to 50% of a diglycidyl ether of bisphenol A having a molecular weight of from about 600 to 2,500; and from about 0.1 to 15 parts by weight of the total resin weight, a cationic photoinitiator; applying the permanent plating resist on the substrate; photopatterning the permanent plating resist to form apertures therein which expose areas of the substrate; and electrolessly plating metal onto the exposed areas of the substrate. The permanent plating resist is useful to protect the substrate areas including for example metallized features on the substrate, from the electroless deposition of metal during electroless plating; thus selective plating of metal is achieved. The permanent plating resist is not degraded by conventional gold or copper electroless baths. The invention also relates to circuitized structures produced by the methods of electroless plating.

Circuitized structures produced by the methods of electroless plating

A structure of and method for producing a multilayer printed or wiring circuit board, and more particularly a method producing so-called z-axis or multilayer electrical interconnections in a hierarchial wiring structure in order to be able to provide for an increase in the number of inputs and outputs (I/O) in comparison with a standard printed wiring board (PWB) arrangement, and a printed wiring board produced by the method.

Printed wiring board structure with z-axis interconnections

The present invention comprises a method of making a circuitized structure. The method comprises the steps of providing a substrate coated with a polymeric dielectric layer, treating the substrate with alkali, baking the substrate to modify the surface of the polymeric dielectric layer, applying a seed layer to the polymeric dielectric layer and applying conductive layer to the seed layer. The invention also comprises a printed circuit structure produced by the method of the present invention.

Method of uniformly depositing seed and a conductor and the resultant printed circuit structure

A method and structure is provided for preventing wetting or bleed of an adhesive, such as an epoxy, onto noble metal wire bond pads on the surface of a dielectric substrate when attaching an I/C chip to the substrate. The method includes treating the wire bond pads with a chemical composition which prevents bleeding onto the surfaces of the wire bond pads by a component of the epoxy. The chemical composition is a chemical which will provide &ldquo;Self-Assembled Monolayers&rdquo; (SAMs) on the surface of the gold. These compositions are characterized by a molecule having at least one group, such as a mercaptan or disulfide, connected to a hydrocarbon moiety, such as a (CH ) chain. The affinity of the thiol or sulfur-containing portion of the molecule chemically bonding with the noble metal provides a relatively strong attachment of the molecule to the metal surface. The hydrocarbon segment presents a surface on the noble metal that has the characteristics of the hydrocarbon portion of the molecule which has a low surface tension, and, thus, prevents wetting of the noble metal by an epoxy adhesive component. The SAMs, once they provide protection from the bleed of the die attach adhesives, self desorb during the wire bonding or soldering temperatures.

Method for preventing adhesive bleed onto surfaces

A novel method of filling apertures in substrates, such as through holes, is provided. The method utilizes a phtoimageable film, and comprises the following steps: applying a photoimagable, hole fill film over the apertures, preferably having a solvent content of 7-18%; reflowing the hole fill film to flow into the apertures; exposing the hole fill film to actinic radiation, preferably ultraviolet light, through a phototool, which preferably has openings slightly larger than the diameter of the apertures; then at least partially curing the hole fill film; and developing the hole fill film to remove the unexposed hole fill film. Thus, the apertures may be selectively filled. After the apertures are filled, the hole fill film is cured. Thereafter, the substrate may be subjected to further processing steps, for example, nubs of cured hole fill film can be removed. If desired, the substrate is circuitized and overplated with gold.

Methods for selectively filling apertures

An electronic package, and method of making the electronic package, is provided. The package includes a semiconductor chip and an multi-layered interconnect structure having a high density interconnect layer such as an allylated surface layer. The semiconductor chip includes a plurality of contact members on one of its surfaces that are connected to the multi-layered interconnect structure by a plurality of solder connections. The multi-layered interconnect structure is adapted for electrically interconnecting the semiconductor chip to a circuitized substrate (eg., circuit board) with another plurality of solder connections and includes a thermally conductive layer being comprised of a material having a selected thickness and coefficient of thermal expansion to substantially prevent failure of the solder connections between said first plurality of electrically conductive members and the semiconductor chip. The electronic package further includes a dielectric material having an effective modulus to assure sufficient compliancy of the multi-layered interconnect structure during operation. The allylated surface layer has the property of being able to withstand thermal stresses that arise during thermal cycling operation of the electronic package.

Electronic package with high density interconnect layer

Structure for preventing adhesive bleed onto surfaces

The present invention comprises a method of making a circuitized structure. The method comprises the steps of providing a substrate coated with a polymeric dielectric layer, treating the substrate with alkali, baking the substrate to modify the surface of the polymeric dielectric layer, applying a seed layer to the polymeric dielectric layer and applying a conductive layer to the seed layer. The invention also comprises a printed circuit structure produced by the method of the present invention.

Method of uniformly depositing seed and a conductor and the resultant

A process of fabricating a circuitized substrate is provided which comprising the steps of: providing an organic substrate having circuitry thereon; applying a dielectric film on the organic substrate; forming microvias in said dielectric film; sputtering a metal seed layer on the dielectric film and in said microvias; plating a metallic layer on the metal seed layer; and forming a circuit pattern thereon.

Integrated manufacturing packaging process

Simple, environmentally friendly developers and strippers are disclosed for free radical-initiated, addition polymerizable resists, cationically cured resists and solder masks and photoresists. Both the developers and the strippers include benzyl alcohol, optionally also including a minor amount of methanol, ethanol, isopropyl alcohol, propylene glycol monomethylacetate, ethylene glycol monomethyl ether, formamide, nitromethane, propylene oxide, or methyl ethyl ketone, acetone and water.

Photoresist develop and strip solvent compositions and method for their

A novel method of filling apertures in substrates, such as through holes, is provided. The method utilizes a photoimageable film, and comprises the following steps: applying a photoimagable, hole fill film over the apertures; reflowing the hole fill film to flow into the apertures; exposing the hole fill film to actinic radiation, preferably ultraviolet light, through a phototool, which preferably has openings slightly larger than the diameter of the apertures; then at least partially curing the hole fill film; and developing the hole fill film to remove the unexposed hole fill film. An advantage of the present method is that the apertures may be selectively filled. After the apertures are filled, the hole fill film is cured, preferably by baking. Thereafter, the substrate is preferably subjected to further processing steps; for example, nubs of cured hole fill film are preferably removed. If desired, the substrate is circuitized. If desired, features are gold plated, such as for example, electrolessly gold plated. The hole fill film preferably has solids which comprise 0 to about 20% of a thixotrope and about 80% to about 100% parts of an epoxy resin system; the epoxy resin system comprises: from about 10% to about 80% of phenoxy polyol resin which is the condensation product of epichlorohydrin and bisphenol A, having a molecular weight of from about 40,000 to about 130,000; from about 20% to about 90% of an epoxidized multifunctional bisphenol A formaldehyde novolac resin having a molecular weight of from about 4,000 to about 10,000; from about 35% to about 50% of a diglycidyl ether of bisphenol A, preferably halogenated, and having a molecular weight of from about 600 to about 2,500; and from about 0.1 to about 15 parts by weight of the total resin weight, a cationic photoinitiator. The invention also relates to circuitized structures produced according to the method.

Methods of selectively filling apertures

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Apalachin, NY, United States of America

Gerald Walter Jones