International Business Machines Corporation

Gerald U Merckel

Jerry D Dixon

Andrew B McNeill

Gerald A Marazas

Robert H Farrell

Akram Bou-Ghannam

William Garrett Verdoorn, Jr

Layton Balliet

Thomas K Pate

Richard N Ames

Joseph A Boscove

Peter Langer

Richard V Ballou

William Craig Troop

Peter B Bandy

Robert V Miller

Stanley M Belyeu

Nicholas J Schwartz

Frederick T Slater

Stanford A Strickland

Paul Magura

Jack D Neely

Stephen A Schmitt

An advanced display system controller is described for use in automotive vehicles. The controller has electronic circuitry to allow it to be programmed to display monochrome or color graphics and text on an all-points-addressable display device such as a CRT or an Electro-Luminescent (EL) Flat panel. The display resolution and scan rates may be programmed differently depending on the display type and size. The vehicle operator controls the display system via a reconfigurable switch system (RSS), such as an Infrared Touch Panel or Mylar Touch Switch Matrix mounted over the face of the display. In addition, external discrete switches may also be attached to the controller. The controller includes a master microprocessor and a slave microprocessor with preferred partitioning of functions and communicates with other parts of the vehicle via two serial data communication links, a Random Access bus and a Poll/Response bus. The design of this controller allows the display characteristics and supported functions to be changed through reconfigurable hardware and software, allowing a broad range of applications in different model automobiles.

Display system for automotive vehicle

A redundant error-detecting addressing code for use in a cache memory. A directory converts logical data addresses to physical addresses in the cache where the data is stored in blocks. The blocks are expanded to include redundant addressing information such as the logical data address and the physical cache address. When a block is accessed from the cache, the redundant addressing is compared to the directory addressing information to confirm that the correct data has been accessed.

Redundant page identification for a catalogued memory

In a data processing system of the type wherein a host processor transfers data to or from a plurality of attachment devices, a cache memory is provided for storing blocks of data which are most likely to be needed by the host processor in the near future. The host processor can then merely retrieve the necessary information from the cache memory without the necessity of accessing the attachment devices. When transferring data to cache from an attachment disk, additional unrequested information can be transferred at the same time if it is likely that this additional data will soon be requested. Further, a directory table is maintained wherein all data in cache is listed at a 'home' position and, if more than one block of data in cache have the same home position, a conflict chain is set-up so that checking the contents of the cache can be done simply and quickly.

I/O Storage controller cache system with prefetch determined by

When transferring data to a cache memory from an attachment data storage device, additional unrequested information can be transferred at the same time if it is likely that this additional data will soon be requested. The average quantity of data transferred to the cache memory in each operation can be automatically and continually varied in order to maximize the performance advantage provided by the cache memory. When a record of data is requested by the host processor, data is transferred to the cache memory from an attachment data storage device in increments of fixed-length data blocks each containing a sequence of data records, with the number of transferred blocks being determined by the position of a requested data record in its respective data block, and the average number of blocks transferred in any one operation being varied by adjusting threshold position values at which second or third data blocks are transferred.

Automatic adjustment of the quantity of prefetch data in a disk cache

A method and apparatus for performing data base searches in which the host processor and main memory are free for other processing tasks between the time that the host processor requests the search until the search results are reported back to the host processor. To commence the search, an input/output controller communicates from the host processor to a record scan circuit values of a skip length, a key length and a data length. While data records are received serially from disk files, within each data record, a length of data equal to the specified skip length is initially skipped. Following this, a search argument is compared with a length of data specified by the key length value. This comparison operation is alternated with skipping of data specified by the data length value until the end of the record is reached or until a specified number of comparisons has taken place. The data record is stored as it is received from the files. If a successful comparison is found within a data record, either the entire data record or a specified portion thereof can be read back through the controller to the host processor.

Associative file processing method and apparatus

An optical coupler includes a transparent sphere having a reflective coating on the surface thereof for reflecting light within the sphere. A light source optical transmission line introduces light into the sphere which radiates directly to output optical transmission lines. The light introduced into the sphere is also reflected one or more times and is then introduced into one of the transmission lines.

Optical coupler for interconnecting two or more optical transmission

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Delray Beach, FL, United States of America

Gerald U Merckel