Qualcomm Incorporated

Emulex Design & Manufacturing Corporation

Gerald Sweeney

Marc M Hoffman

Deepak Mathew

Srijesh Sudarsanan

Sundar Rajan Balasubramanian

Andrew P Moroney

Hongfeng Dong

Yurong Sun

Mansi Jain

Kenneth Baumoel

Seyedmehdi Sadeghzadeh

James Lee

An electronic device receives a single instruction to apply a neural network operation to a set of M-bit elements stored in one or more input vector registers to initiate a sequence of computational operations related to a neural network. In response to the single instruction, the electronic device implements the neural network operation on the set of M-bit elements to generate a set of P-bit elements by obtaining the set of M-bit elements from the one or more input vector registers, quantizing each of the set of M-bit elements from M bits to P bits, and packing the set of P-bit elements into an output vector register. P is smaller than M. In some embodiments, the neural network operation is a quantization operation including at least a multiplication with a quantization factor and an addition with a zero point.

Instruction set architecture for neural network quantization and packing

A device includes a vector register file, a memory, and a processor. The vector register file includes a plurality of vector registers. The memory is configured to store a permutation instruction. The processor is configured to access a periodicity parameter of the permutation instruction. The periodicity parameter indicates a count of a plurality of data sources that contain source data for the permutation instruction. The processor is also configured to execute the permutation instruction to, for each particular element of multiple elements of a first permutation result register of the plurality of vector registers, select a data source of the plurality of data sources based at least in part on the count of the plurality of data sources and populate the particular element based on a value in a corresponding element of the selected data source.

Permutation instruction

A system enables communication between a first network having a first network protocol and a second network having a second network protocol. At least one of the first and second networks is a storage area network. The system includes first and second data ports for receiving, from the first network, input data and state information respectively. A microsequencer is configured to translate the input data, which is expressed in the first network protocol, into corresponding data expressed in the second network protocol. This translation is performed in part on the basis of the state information.

System for communication with a storage area network

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Chelmsford, MA, United States of America

Gerald Sweeney