International Business Machines Corporation

Gerald Strevig, Iii

Jesse Peter Surprise

Shawn Kollesar

Adam P Matheny

Christopher J Berry

David S Wolpert

Robert Mahlon Averill, Iii

Michael Alexander Bowen

Michael Kazda

Joseph J Palumbo

Frank Malgioglio

Mitchell R DeHond

Alice Hwajin Lee

Jose Luis Pontes Correia Neves

Amanda Christine Venton

Adam R Jatkowski

Chris Aaron Cavitt

Chaobo Li

Ryan M Nett

Sean Salisbury

Dina Hamid

Aspects of the invention include methods, systems, and computer program products for integrated circuit development using cross-hierarchy antenna condition verification. A method includes obtaining a design of a hierarchical macro distributed between multiple files for an integrated circuit and analyzing, by a design verification tool, a route between at least one child macro and at least one pin of the hierarchical macro as defined in the files. The method further includes determining, by the design verification tool, a plurality of connection characteristics of the at least one child macro and the at least one pin forming the route and calculating, by the design verification tool, an antenna condition for the route based on the connection characteristics. The design of the hierarchical macro is adjusted to remove a violation of an antenna rule based on determining that the antenna condition of the route violates the antenna rule.

Cross-hierarchy antenna condition verification

Examples described herein provide a computer-implemented method that includes identifying, by a processing device, a victim/aggressor pair of nets for an integrated circuit. The method further includes severing nets of the victim/aggressor pair of nets. The method further includes swapping severed segments of the nets. The method further includes rerouting the nets subsequent to swapping the severed segments of the nets.

Noise impact on function (NIOF) reduction for integrated circuit design

Methods, systems and computer program products for improved placement of a clock gating latch are provided. Aspects include identifying a clock gating latch that is designated to control a local clock buffer. Aspects also include determining a plurality of data latches that are designated to be controlled by the local clock buffer. Aspects also include determining positions of the plurality of data latches within a layout. Aspects also include determining a position of the clock gating latch within the layout based on the positions of the plurality of data latches within the layout.

Clock gating latch placement

Methods, systems and computer program products for improved metal fill shape removal from selected nets are provided. Aspects include determining a first set and second set of timing characteristics of a first and second circuit design, respectively. The first circuit design does not include metal fill shapes around a plurality of nets, whereas the second circuit design does include metal fill shapes around a plurality of nets. Aspects also include identifying a set of candidate nets based on a comparison of the first set of timing characteristics to the second set of timing characteristics. The set of candidate nets are nets that are candidates for metal fill shape removal. Aspects include generating a third circuit design by removing one or more metal fill shapes positioned around each net of the set of candidate nets that are positioned within a radius of removal.

Metal fill shape removal from selected nets

Methods, systems and computer program products for providing cross-hierarchical block pin placement are provided. Aspects include designating potential pin placements by aligning output pins of each of a first set of bottom-level hierarchical blocks positioned within one or more middle-level hierarchical blocks to an edge of a respective middle-level hierarchical block. Responsive to determining that each of a first subset of a second set of bottom-level hierarchical blocks having input pins that correspond to the output pins of the first set of bottom-level hierarchical blocks are positioned within a respective middle-level hierarchical block that has a cross hierarchical alignment, aspects include placing pins at one or more of the potential pin placements. Aspects also include placing a set of pins based on aligning input pins of a second subset of the second set of bottom-level hierarchical blocks to an edge of a respective middle-level hierarchical block.

Cross-hierarchical block pin placement

Methods, systems and computer program products for providing wire orientation-based latch shuddling are provided. Aspects include determining a classification of each latch of a plurality of latches as having a vertical orientation, a horizontal orientation or a mixed orientation. Aspects also include clustering the plurality of latches into one or more clusters based on the classifications of the plurality of latches. Each of the one or more clusters includes a unique set of latches of the plurality of latches. Aspects also include shuddling each of the one or more clusters around a local clock buffer within a layout. Each cluster of the one or more clusters is shuddled in a configuration around the local clock buffer based on the classifications of the corresponding unique set of latches of the plurality of latches.

Wire orientation-based latch shuddling

Methods, systems and computer program products for providing improved placement and connectivity of local clock buffer controllers are provided. Aspects include determining positions of a plurality of centroid locations within a circuit design based on positions of a plurality of latches within the circuit design. Aspects also include modifying the circuit design to place a local clock buffer controller at each of the plurality of centroid locations within the circuit design. Aspects also include connecting each of a plurality of local clock buffers within the circuit design to a nearest local clock buffer controller.

Local clock buffer controller placement and connectivity

A data processing system to implement wiring/silicon blockages via parameterized cells (pCells) includes a front end-of-line placement/blockage (FEOL P/B) controller to generate a placement blockage based on an input parameter corresponding to a physical design of an integrated circuit (IC). The FEOL P/B outputs a placement blockage parameter that is stored in a wire track allocation database to indicate the placement blockage. A back end-of-line wiring track (BEOL WT) controller generates a wire track blockage of the IC. A BEOL power track (BEOL PT) controller generates a metal blockage within the wire track blockage. A combination of the metal blockage and the wire track blockage defines a parent-child contract to enable concurrent physical design of the IC without creating shorts and overlaps in a child block of the IC.

Growing community of inventors

Cedar Park, TX, United States of America

Gerald Strevig, Iii