Intel Corporation

Gerald S Pasdast

Adel A Elsherbini

Zuoguo Wu

Shawna M Liff

Johanna M Swan

Debendra Das Sharma

Lakshmipriya Seshan

Swadesh Choudhary

Narasimha Lanka

Mahesh U Wagh

Narasimha R Lanka

Van H Le

Patrick R Morrow

Nevine Nassif

Tejpal Singh

Carleton L Molnar

Krishnakanth Venkata Sistla

Venkatraman Iyer

Ankush Varma

Zhiguo Qian

Yen-Cheng Liu

Dheeraj R Subbareddy

George Zacharias Chrysos

Vedaraman Geetha

Mahesh K Kumashikar

Jeffrey D Chamberlain

William R Halleck

Srikanth Nimmagadda

John R Ayers

Sathya Narasimman Tiagaraj

Peipei Wang

Siva Soumya Eachempati

Aleksandar Aleksov

Feras Eid

Robert G Blankenship

Kimin Jun

Robert J Safranek

Krishna Bharath

Mohammad Enamul Kabir

Ananthan Ayyasamy

Han Wui Then

Mauro J Kobrinsky

Edward Allyn Burton

David M Lee

Kevin P O'brien

Todd A Hinck

Lip Khoon Teh

Sridhar Muthrasanallur

Xiaobei Li

Mauro Kobrinksy

Georgios C Dogiamis

Dmitri E Nikonov

Min Huang

Tanay Karnik

Nasser A Kurd

William J Lambert

Su Wei Lim

Peter Onufryk

Ishwar Agarwal

Jeff Jones

Dimitrios Ziakas

Julien Sebot

Mark S Birrittella

Greg F Taylor

Neelam Chandwani

Robert J Munoz

Jayen J Desai

Daniel Krueger

Paul F Newman

Nicolas Butzen

Azydee Hamid

Anoop Kumar Upadhyay

Yingyu Miao

Chee Bow Lim

Vivek Kumar Rajan

Timothy Francis Schmidt

Vikrant Thigle

Juan Zeng

Ahmad Siddiqui

Vijay Anand Mathiyalagan

Arun Chandrasekhar

Anand Haridass

Xiaobel Li

Ishaan S Shah

Zuoguo J Wu

Embodiments described herein may include apparatus, systems, techniques, or processes that are directed to on-package die-to-die (D2D) interconnects. Specifically, embodiments herein may relate to on-package D2D interconnects for memory that use or relate to the Universal Chiplet Interconnect Express (UCIe) adapter or physical layer (PHY). Other embodiments are described and claimed.

On-package die-to-die (D2D) interconnect for memory using universal chiplet interconnect express (UCIe) PHY

Embodiments herein relate to a clock interpolation system. The system may be configured to identify, at a change in logical state of a recovered clock signal, a logical state of a first signal when the first signal is delayed by a delay value. The system may be further configured to identify, at a change in logical state of a second signal, a logical state of the clock signal when the clock signal is delayed by the delay value. Based on the two identifications, the delay value and/or a timing of the clock signal may be adjusted. Other embodiments may be described and/or claimed.

Clock interpolation system for eye-centering

Protocol layer logic in a protocol stack receives an indication that a particular mode is to be utilized on a die-to-die (D2D) link connecting a first device to a second device. The protocol layer logic generates data to be sent on the D2D link to adapt the particular data format to a flit format defined for use on the D2D link in the particular mode, the flit format comprises providing a set of reserved fields to be completed by an adapter block positioned between the protocol circuitry and a physical layer block. The data in the flit format is sent to the data to the adapter block to prepare the data for transmission over the D2D link.

Die-to-die interconnect protocol layer

A retimer includes a first port to couple to a die over a first interconnect, where the first interconnect includes a defined set of lanes and utilizes a first communication technology, and the die is located on a first package with the retimer. The retimer further includes a second port to couple to another retimer over a second interconnect, where the second interconnect utilizes a different second communication technology, and the second retimer is located on a different, second package to facilitate a longer reach communication channel.

Retimers to extend a die-to-die interconnect

In one embodiment, a first die comprises: a first die-to-die adapter to communicate with first protocol layer circuitry via a flit-aware die-to-die interface (FDI) and first physical layer circuitry via a raw die-to-die interface (RDI), where the first die-to-die adapter is to receive message information comprising first information of a first interconnect protocol; and the first physical layer circuitry coupled to the first die-to-die adapter. The first physical layer circuitry may be configured to receive and output the first information to a second die via an interconnect, the first physical layer circuitry comprising a plurality of modules, each of the plurality of modules comprising an analog front end having transmitter circuitry and receiver circuitry. Other embodiments are described and claimed.

Standard interfaces for die to die (D2D) interconnect stacks

A microelectronic assembly is provided comprising: a first plurality of integrated circuit (IC) dies in a first layer; a second plurality of IC dies in a second layer between the first layer and a third layer; and a third plurality of IC dies in the third layer. In some embodiments, the second plurality of IC dies comprises IC dies in an array of rows and columns, each IC die of the second plurality of IC dies is coupled to more than one IC die of the first plurality of IC dies, and the third plurality of IC dies is to provide electrical coupling between adjacent ones of the second plurality of IC dies.

Fine-grained disaggregated server architecture

Embodiments herein relate to a die of a multi-die package, wherein the die is coupled with another die via a die-to-die (D2D) interconnect link. The die may transmit a data signal to the other die via a data lane of the D2D interconnect link. The die may further transmit, concurrently with the data signal, a valid signal to the other die via a valid lane of the D2D interconnect link. The valid signal may change logical state at least once during the transmission of the data signal. Other embodiments may be described and claimed.

Valid signal for latency sensitive die-to-die (D2D) interconnects

In one embodiment, an apparatus includes: a die-to-die adapter to communicate with a protocol layer and physical layer circuitry, and the physical layer circuitry coupled to the die-to-die adapter, where the physical layer circuitry is to receive and output first information to a second die via an interconnect. The physical layer circuitry, after a reset flow for the first die, is to: perform a sideband initialization of a sideband interface of the interconnect to detect that the second die has completed a reset flow for the second die; and after the sideband initialization, perform a mainband initialization of a mainband interface of the interconnect at a lowest speed, and thereafter perform a mainband training of the mainband interface at a negotiated data rate. Other embodiments are described and claimed.

Link initialization training and bring up for die-to-die interconnect

Embodiments of the present disclosure provide a microelectronic assembly comprising: an integrated circuit (IC) die in a first layer and a plurality of IC dies in a second layer, at least two adjacent IC dies in the plurality being electrically coupled along their proximate edges by the IC die. The first layer and the second layer are electrically and mechanically coupled by interconnects having a pitch of less than 10 micrometers between adjacent interconnects, and the IC die comprises capacitors and voltage regulator circuitry.

Power delivery through capacitor-dies in a multi-layered microelectronic assembly

Embodiments herein relate to action that are to be taken on various lanes of a die-to-die (D2D) interconnect in the event of clock-gating. Specifically, based on identification that a clock-gating event is to occur, physical layer (PHY) logic may direct PHY electrical circuitry to set the state of various of the lanes. In some embodiments, different actions may be taken based on whether the D2D interconnect is terminated or unterminated. Other embodiments may be described and claimed.

Clock-gating in die-to-die (D2D) interconnects

Techniques and mechanisms for high interconnect density communication with an interposer. In some embodiments, an interposer comprises a substrate and portions disposed thereon, wherein respective inorganic dielectrics of said portions adjoin each other at a material interface, which extends to each of the substrate and a first side of the interposer. A first hardware interface of the interposer spans the material interface at the first side, wherein a first one of said portions comprises first interconnects which couple the first hardware interface to a second hardware interface at the first side. A second one of said portions includes second interconnects which couple one of first hardware interface or the second hardware interface to a third hardware interface at another side of the interposer. In another embodiment, a metallization pitch feature of the first hardware interface is smaller than a corresponding metallization pitch feature of the second hardware interface.

Composite interposer structure and method of providing same

In one embodiment, an apparatus comprises a first die that includes: a die-to-die adapter comprising a plurality of first registers, the die-to-die adapter to communicate with protocol layer circuitry via a flit-aware die-to-die interface (FDI) and physical layer circuitry via a raw die-to-die interface (RDI), wherein the die-to-die adapter is to receive message information of a first interconnect protocol; and the physical layer circuitry coupled to the die-to-die adapter, the physical layer circuity comprising a plurality of second registers, where the physical layer circuitry is to receive and output the message information to a second die via an interconnect having a mainband and a sideband. During a test of the apparatus, the sideband is to enable access to information in at least one of the plurality of first registers or at least one of the plurality of second registers. Other embodiments are described and claimed.

Compliance and debug testing of a die-to-die interconnect

A port is to couple to another die over a die-to-die (D2D) link and includes physical layer (PHY) circuitry including a first number of sideband lanes to carry data for use in training and management of the D2D link, and a second number of mainband lanes to implement a main data path of the D2D link. The mainband lanes include a forwarded clock lane, a valid lane, and a plurality of data lanes. A logical PHY coordinates functions of the sideband lanes and the mainband lanes.

Die-to-die interconnect

In one embodiment, an apparatus includes: a die-to-die adapter to communicate with protocol layer circuitry and physical layer circuitry; and the physical layer circuitry coupled to the die-to-die adapter, where the physical layer circuitry is to receive and output first information to a second die via an interconnect. The physical layer circuitry may include: a first sideband data receiver to couple to a first sideband data lane and a first sideband clock receiver to couple to a first sideband clock lane; and a second sideband data receiver to couple to a second sideband data lane and a second sideband clock receiver to couple to a second sideband clock lane. The physical layer circuitry may assign a functional sideband comprising: one of the first or second sideband data lanes; and one of the first or second sideband clock lanes. Other embodiments are described and claimed.

Sideband interface for die-to-die interconnects

In one embodiment, an apparatus includes PHY circuitry to implement a PHY-based retry technique, e.g., in die-to-die interfaces. The PHY circuitry includes a retry buffer to buffer data provided by the interface controller and error detection code generation circuitry to generate error detection codes based on input data. The PHY circuitry is to implement the retry technique by detecting a stall signal asserted by another apparatus across the channel, causing the error detection code generation circuitry to generate error detection codes based on data in the retry buffer, and transmitting the data from the retry buffer and its corresponding error detection codes across the channel to the other apparatus.

PHY-based retry techniques for die-to-die interfaces

Growing community of inventors

San Jose, CA, United States of America

Gerald S Pasdast