Northrop Grumman Systems Corporation

Trw Limited

Gerald R Fischer

Douglas S Cockfield

Andrew Donovan Smith

Harvey L Berger

Scott M Takahashi

Marlon E Marquez

Roger A Davidheiser

Cyrus Dhalla

Talley J Allen

Matthew M D'Amore

Ken K Tsai

Akop Gazdzhyan

Neal J Schneier

Jonathan Krauss

George E Avera

An exemplary beam alignment system uses beam sensors that generate electrical signals corresponding to an amount of beam striking each sensor. An offset correction circuit determines an amount of undesired beam striking the sensors. The offset correction circuit subtracts the undesired beam value from each of the electrical signals to generate respective corrected values. X and Y signals, generated based on the corrected values, determine an X-axis and Y-axis location of the beam on the beam sensors. Position control signals, generated based on the X and Y signals, control the position of the beam relative to the sensors resulting in a corresponding X-axis and Y-axis location of the beam on the sensors. This provides compensation for changes in orientation of the incoming beam relative to the sensors to maintain the beam location on the sensors.

Beam alignment system

An embodiment generates a composite high speed clock with embedded frame synchronization using simple digital encoding of a high speed reference clock. The high speed reference clock and self-aligned frame synchronization signal are recovered by standard logic gate circuitry. The encoding and decoding circuits are comprised of basic digital logic gates with low propagation delay skew and timing jitter. The encoded clock is easier to transmit from source unit to destination unit over common transmission media (i.e., digital transceivers, amplifiers, splitters, connectors and coaxial cable) because only a single interface is required and because the encoding scheme reduces the composite clock to a minimal transmission bandwidth with constrained waveform harmonic content, relative to a low frequency frame sync with fast rise time that requires a broadband transmission media.

Clock and frame synchronization carried as a single composite signal allows the use of a single transmission line with a narrower bandwidth

A clock recovery circuit for providing clock recovery from a burst signal that is periodically present and absent in a noisy channel. The recovery circuit includes an outer main tracking second-order phase locked loop (PLL) having an analog phase detector, a digital loop filter, and an analog/digital hybrid numerically controlled oscillator (NCO) that operates so that the clock recovery frequency is 'frozen' to its last value from the previous burst and the phase detector is disabled during the gaps between data bursts. The NCO is implemented with an inner loop PLL that operates as a high resolution synthesizer having a low internal control bandwidth that preserves VCO phase noise. The outer main loop achieves a higher control bandwidth through direct tuning of the inner loop VCO with the outer loop tuning signal.

Signal phase tracking with high resolution, wide bandwidth and low phase noise using compound phase locked loop

A reduced power consumption actuator drive circuit that includes separate circuit power paths for different portions of the signal spectrum for applications in which lower frequencies have high amplitudes. The low frequency circuit paths use higher power supply voltages at lower currents and the high frequency circuit paths use lower power supply voltages at higher currents. In one embodiment, the drive circuit drives a nutator that employs a resonating circuit that maintains actuator motion with reduced energy supplied by the power supply.

Method and apparatus for producing optical tracking and nutation at high frequencies with low power

A symbol clock recovery circuit for recovering a symbol clock in an M-ary pulse position modulation (PPM) signal. The recovery circuit includes a largest magnitude comparison circuit that selects a largest magnitude signal value from a group of M signal values aligned with a hypothesis symbol boundary location and the average of that largest magnitude value is compared with a threshold, or with results from other boundary location hypotheses, or with both, to determine the true position of the symbol boundary.

Method for symbol clock recovery in pulse position modulation (PPM) systems

An amplitude and phase modulation circuit for modulating an M-ary digital signal having pulses onto a carrier wave for transmission by direct digital synthesis. The modulation circuit includes a digital source that generates a digital signal including pulses representing logical 1s and no pulses representing logical zeros, where a group of M pulses represents a constellation point to be transmitted. The modulation circuit further includes a phase control circuit that provides phase control and an amplitude control circuit that provides pulse width control for the constellation point to be transmitted. A saturated amplifier amplifies the phase and amplitude controlled digital signal and a filter integrates and averages the digital signal to remove noise from the signal so as to convert the digital signal to an analog signal, where the digital source operates to reduce the amplifier power consumption requirements.

Amplitude and phase shift keying modulation for saturated amplifier systems

A plurality of differential encoders encodes a plurality of parallel data bit streams. XOR gates interleave the outputs of the differential encoders forming a single high speed differentially encoded bit stream with a data rate that is the sum of the data rate of the parallel data bit streams. The high speed data stream provides a single differentially encoded input to a differential phase shift keying modulator that generates symbols for a high speed optical communication system.

High speed differential encoder and interleaver

A method for ultra wideband (UWB) communication in which UWB pulses encode binary data as either normal or inverted (anti-podal) pulses. In the case of pulses of a carrier signal, each pulse has the carrier signal either inverted or in phase, that is, shifted by 180&#xb0;, or not. For example, a binary '1' may be encoded as a normal or non-inverted pulse and a binary '0' as an inverted pulse. After each carrier pulse is rectified and filtered, detection is effected using a threshold value of zero, resulting in increased immunity to noise, compared with detection of unidirectional pulses. In one aspect of the invention, data pertaining to multiple communication channels are encoded in time-divided portions of each UWB pulse.

Bipolar waveform modulation for ultra wideband (UWB) communication networks

A switched low pass filter ( ) minimizes transients generated during filter switching events and eliminates active circuit random noise. The switched low pass filter ( ) includes a filter input terminal ( ) for receiving an input base band signal, and an RC circuit (R , C , S , S ) for receiving the input base band signal and for passing only a filtered portion of the input base band signal depending on a wide, mid or narrow band mode of filter operation. The switched low pass filter ( ) also includes a transient reduction circuit ( ) in switchable communication with the RC circuit (R , C , S , S ) for minimizing transients and switching events caused by transitioning to the mid and narrow band modes of filter operation.

Low noise switched low pass filter with benign transients

A phase locked loop ( ) for generating a variable output frequency signal. The phase locked loop ( ) includes a controlled oscillator ( ) to generate the variable output frequency signal in response to a tune signal. A phase detector ( ) is activable in response to a gating signal ( ) to generate an error signal representing a difference between a reference frequency signal and the variable output frequency signal. A loop filter ( ) having a filter characteristic, filters the error signal and generates the tune signal. An offset cancellation circuit ( ) is coupled to the loop filter ( ). In response to an error signal representing phase offset of the phase locked loop ( ), the offset cancellation circuit ( ) supplies a compensating signal to reduce the phase offset.

Phase locked loop with offset cancellation

The present invention provides a phase locked loop ( ) for generating a variable output frequency signal. The phase locked loop ( ) includes a controlled oscillator ( ) to generate the variable output frequency signal in response to a tune signal. A feedback frequency divider ( ) coupled to the controlled oscillator ( ) is operable to generate a divided frequency signal from the variable output frequency signal. A phase detector ( ) generates an error signal representing a difference between a reference frequency signal and the divided frequency signal. A sample and hold circuit ( ) is activable in response to a gating signal ( ) derived from the reference frequency, to sample the error signal and generate a sampled signal. A loop filter ( ) filters the sampled signal and generates the tune signal.

Phase locked loop using sample and hold after phase detector

A phase locked loop ( ) for generating an output frequency signal. The phase locked loop ( ) includes a controlled oscillator ( ) to generate the output frequency signal in response to a tune signal. A phase detector ( ) generates an error signal representing a difference between a reference frequency signal and the output frequency signal. A loop filter ( ) having a filter characteristic, filters the error signal and generates the tune signal. The loop filter ( ) includes a bandwidth switching circuit ( ) to vary the filter characteristics. A charge cancellation circuit ( ) is coupled to the loop filter ( ). In response to the error signal, the charge cancellation circuit ( ) cancels errors associated with the bandwidth switching circuit.

Phase locked loop with charge injection cancellation

A family of logic circuits using nonhysteretic superconducting quantum interference devices (SQUIDs) connected together to perform various functions using a common operating principle. Each circuit has an output line, first and second power supply lines having first and second voltage states, and input lines that can have one of the two voltage states. A pull-up circuit, having at least one SQUID, is connected between the output line and the first power supply line, and the input lines are coupled to the pull-up circuit in such a manner as to pull the output line to the first voltage state only if the input lines conform with a selected combination of voltage states. A pull-down circuit, also having at least one SQUID, is connected between the output line and the second power supply line, to pull the output line to the second voltage state only when input lines do not conform with the selected combination of voltage states. A single configuration of SQUIDs can be connected to perform any of six different basic Boolean logic functions on signals applied to the input lines. Additional SQUIDs allow the performance of more complex logic functions. A slightly different arrangement of SQUIDs operates as a two-port random access memory cell.

Growing community of inventors

Playa Del Rey, CA, United States of America

Gerald R Fischer