International Business Machines Corporation

Invecas, Inc.

Gerald P Pomichter

John Atkinson Fifield

John Edward Barth, Jr

Harold Pilo

Jeanne P Bickford

Mark Steven Styduhar

Jeffrey Scott Zimmerman

Jason Edward Rotella

Michael Lee

Bernhard J Wunder

A content addressable memory ('CAM') field enabling logic comprises fields and field enable logics. The fields each have local match lines and a corresponding field enable control for enabling the respective field. The field enable logics are serially connected. Each of the fields is coupled to a corresponding one of the field enable logics via the respective local match lines. The corresponding field enable control for each of the fields is coupled to the corresponding one of the field enable logic and to any ones of the field enable logics that come after the corresponding one of the field enable logic along the serially-connected field enable logics.

TCAM field enable logic

A semiconductor structure including a device configured to receive an input data-word. The device including a logic structure configured to generate an encrypted data-word by encrypting the input data-word through an encrypting operation. The device further including an eFuse storage device configured to store the encrypted data-word as eFuse data by blowing fuses in accordance with the encrypted data-word.

Electronically programmable fuse security encryption

Aspects of the invention provide for masking a current profile of a one-time programmable (OTP) memory. In one embodiment, a circuit includes: a first one-time programmable (OTP) memory configured to receive a data input for a plurality of address fields; and a second OTP memory configured to receive an inverse of the data input for a plurality of address fields, wherein a current profile for a programming supply for the first OTP memory and the second OTP memory is masked, such that the data input for the first OTP memory is undetectable.

Protection of one-time programmable (OTP) memory

Systems and methods receive a design of a circuit layout. The circuit layout has some available spaces. Such systems and methods automatically insert capacitor arrays in the specified spaces. Each of the capacitor arrays has capacitor cells, and each of the capacitor cells has capacitor structures and a buried implant. The process of inserting the capacitor arrays comprises a process of forming the capacitor arrays to either: grow the capacitor arrays to the size of the specified spaces; grow the capacitor arrays to a specified capacitance value within the restriction of the length dimension or the width dimension of the specified spaces; or grow the capacitor arrays to a specified capacitance value, irrespective of dimensional length dimension or width dimension limitations (where the only limitations are the dimensions of the specified space).

Circuit design with growable capacitor arrays

An on-chip clock multiplier for outputting a fast clock that is approximately a predetermined multiple n of a slow clock. The multiplier utilizing a high-speed oscillator to generate a high-frequency base signal. A lower frequency signal is generated using the high-frequency base signal as a function of the output of a rollover counter that counts from a seed value to a terminal value. A saturation counter is used to determine whether no more than n pulses of the lower frequency signal occur within a single cycle of the slow clock. If not, the lower frequency signal is iteratively slowed by changing the seed value until no more than n pulses of the lower frequency signal occur within a single cycle of the slow clock. When this iteration is done, the fast clock having a frequency that is approximately n times the frequency of the slow clock is output.

Clock multiplier structure for fixed speed testing of integrated circuits

An adjustable clock multiplier circuit is disclosed which is believed to be of advantage for inexpensively and locally generating an adjustable high frequency clock, such as may be useful for built-in self test of an embedded memory element of a digital logic integrated circuit. The clock multiplier circuit uses a pulse generator of the monostable type to generate a pulse in response to the leading edge of an input clock signal. The pulse is delayed through a programmable delay circuit and then provided as a feedback input to the pulse generator. In such manner, an output clock signal comprised of a train of pulses is generated during a cycle of the input clock signal. A counter increments a count in response to pulses generated in this way. When the pulse count is too high, a limiter outputs an ADJUST DOWN signal which slows down the output cycle time of the clock multiplier. When the pulse count is too low, the limiter outputs an ADJUST UP signal which speeds up the output cycle time of the clock multiplier. The ADJUST DOWN/UP signals are preferably provided to a register which maintains and outputs a string of control signals for controlling a set of delay elements within a programmable delay circuit. The programmable delay circuit optionally includes a tap point multiplexer for varying the number of delay elements in the delay path, to provide greater range of frequency multiple and faster lock.

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Fairfax, VT, United States of America

Gerald P Pomichter