Freescale Semiconductor,inc.

Gerald P Miaille

Julian Aschieri

Zhou Zhixu

Brandt Braswell

Ludovic Oddoart

Michael L Gomez

Christian J Rotchford

Boris Razmyslovitch

Jiangbo Gan

An embodiment of an electronic system includes a digital audio amplifier having a continuous time modulator adapted to generate a difference signal between an audio bitstream and a feedback signal, and to perform a modulation process on the difference signal to generate an input pulse modulated signal, a class D output stage adapted to receive, quantize, and amplify the input pulse modulated signal to generate an output pulse modulated signal, and a feedback path adapted to provide the output pulse modulated signal as the feedback signal to the continuous time modulator. Another embodiment includes a class AB output stage adapted to receive and amplify an input digital audio signal to generate an analog output signal, and circuitry adapted to enable the digital audio amplifier to be configured to enable the class AB output stage and to disable the class D output stage.

Digital audio amplifiers, electronic systems, and methods

Methods and corresponding systems for calibrating a digital-to-analog converter include selecting first and second code regions in the digital-to-analog converter, wherein the first and second code regions are separated by a boundary. Thereafter a waveform sequence is input into the digital-to-analog converter, wherein the waveform sequence has a zero offset at the boundary. Then a relative compensation value between the first and second code regions is adjusted to reduce a distortion in an output of the digital-to-analog converter. A magnitude of a third harmonic distortion of the waveform sequence can be used to measure distortion in the output. Adjusting the relative compensation can include converting the output of the digital-to-analog converter to a digital sequence, filtering the digital sequence, and measuring a harmonic distortion in the digital sequence.

Calibrating a digital-to-analog converter

A multi-mode analog-to-digital converter includes a delta-sigma analog-to-digital converter circuit configured to receive the analog input and produce a digital bit-stream associated therewith, the delta-sigma analog-to-digital converter including at least one integrator configured to reset to an initial state in response to a reset signal A digital filter circuit is configured to receive the digital bit-stream and produce two filtered outputs derived from the digital bit-stream. During one mode (e.g., a DC mode) the delta-sigma analog-to-digital converter circuit is configured to receive the reset signal and produce the digital bit-stream for a predetermined number of clock cycles, and the digital output corresponds to the first filtered output. In another mode (e.g., an AC mode), the delta-sigma analog-to-digital converter is configured to continuously produce the bit-stream, and the digital output corresponds to the second filtered output.

Methods and apparatus for a multi-mode analog-to-digital converter

An accumulated current counter () includes a sense resistor () configured for being coupled in series between an electronic circuit () and a power source (). The sense resistor is further for use in sensing a voltage (V) across the sense resistor as a function of a current (Ibatt) provided via the power source. An incremental counter () is coupled to the sense resistor for incrementally counting an amount of current, corresponding to an average value of charge Q, going (i) into or (ii) out of the power source. A register () accumulates a representation of the incrementally counted current. In one embodiment, the representation of incrementally counted current corresponds to a remaining power source life in hours and minutes.

Accumulated current counter and method thereof

A low drop-out voltage regulator having a pass device (Mp), an error amplifier (M-M) and a double regulation loop including DC feedback loop (R, R) and an AC feedback loop (Rf, Cf) including a high pass filter (Cf). Combining these two loops creates an ultra low frequency internal pole which makes the regulator stable substantially independent of the output bypass capacitor's value. This provides the following advantages: allows the use of very low bypass capacitors; allows to extend the PSRR frequency behavior; allows an increase in the regulator's efficiency (reduced power consumption on heavy loads).

Growing community of inventors

Chandler, AZ, United States of America

Gerald P Miaille