Honeywell Information Systems Inc.

Gerald N Winfrey

Minoru Inoshita

Joseph L Ryan

John P Stafford

Frederick E Kobs

In a terminal system comprising a central processor subsystem, a memory subsystem and a plurality of peripheral subsystems, all connected in common to a system bus, the system bus timing is divided into a plurality of fixed times including a central processor (CPU) bus cycle and a plurality of Direct Memory Access (DMA) bus cycles. The central processor subsystem communicates with the memory subsystem during CPU bus cycles and the peripheral subsystems communicate with the memory subsystem on DMA bus cycles. Particular peripheral subsystems are assigned to particular DMA channels. These DMA channels communicate with the memory subsystem on particular DMA bus cycles which are operative in a revolving priority, with the first DMA bus cycle occuring after the last DMA bus cycle of the previous sequence of DMA bus cycles. A plurality of peripheral subsystems are wired to a particular DMA channel in a daisy chain fashion with the peripheral subsystem wired closest to the system bus having top priority. The peripheral subsystem having top priority may be wired either to relinquish the assigned DMA bus cycle after communicating with memory or 'hog' the assigned DMA bus cycle.

Direct memory access revolving priority apparatus

Each row of video information in a display memory includes a linking character code followed by address codes representative of the address location in such display memory of a first data character of a next row of video information displayed on the CRT screen. Both row insertions and deletions may be accommodated by changing address codes under firmware control without requiring the complete rewrite of video information stored in the display memory.

Hardware-firmware CRT display link system

A cathode ray tube display terminal system includes a central processor subsystem and a number of certain peripheral subsystems all of which are coupled in common to a system bus. Apparatus in the central processor subsystem receives interrupt request signals from certain of the peripheral subsystems and on a predetermined priority basis modifies an address generated by the central processor subsystem in dependence upon which of the requesting certain peripheral subsystems has the highest priority. The modified address, called a vectored address points to a firmware subroutine stored in a memory subsystem which is also coupled to the system bus and which processes the interrupt from the highest priority cetain peripheral subsystem. Other peripheral subsystems coupled to the system bus generate a single interrupt signal which is also applied to the apparatus in the central processor system. The highest priority other peripheral subsystem generating the single interrupt signal responds to an interrupt acknowledge signal from the central processor subsystem by sending address signals to the apparatus which are used to modify the address generated by the central processing subsystem so as to produce the vectored address.

CRT display terminal priority interrupt apparatus for generating

A microprocessor controlled cathode ray tube display system has a plurality of peripheral devices all connected in common to a system bus. Apparatus in each peripheral device activates a single interrupt signal. A single acknowledge response signal to all the devices enables the interrupting device to place its address signals on the system bus thereby initiating a firmware routine for making the interrupting device operative with the system.

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Billerica, MA, United States of America

Gerald N Winfrey