Cypress Semiconductor Corporation

On Semiconductor Image Sensor

Gerald LePage

Tomas Geurts

Bart Dierickx

A pixel structure having a shielded storage node. A pixel comprises a sample transistor coupled to a light detecting stage. The sample transistor comprises an inner junction region surrounding and coupled to a storage node and a gate disposed around at least three sides of the inner junction region that operates as a charge barrier to shield the storage node. A memory capacitor is coupled to the storage node.

Pixel structure having shielded storage node

A time delayed integration image sensor provides over-sampled image data on a time-shared column bus to maintain data synchronization.

Time delayed integration CMOS image sensor with zero desynchronization

An analog-to-digital converter (ADC) architecture to implement a non-linear flash ADC. The apparatus includes a non-linear resistor, a non-linear comparator, and an inverse non-linear encoder. The non-linear resistor has an input and a plurality of non-linear voltage outputs. The non-linear comparator ladder is coupled to the plurality of non-linear voltage outputs of the non-linear resistor. The non-linear comparator ladder includes a bank of comparators to compare an input signal to each of a plurality of non-linear voltage signals corresponding to the plurality of non-linear voltage outputs. The inverse non-linear encoder is coupled to the non-linear comparator ladder. The inverse non-linear encoder generates a digital output code based on the input signal and the plurality of non-linear voltage signals.

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Wavre, Belgium

Gerald LePage