Juniper Networks, Inc.

Cavium, Inc.

Marvell Asia Pte., Ltd.

Gerald Lampert

Srihari Raju Vegesna

Craig R Frink

Steven W Aiken

Bryan Chin

Nitin Prakash

Shubhendu Sekhar Mukherjee

David Albert Carlson

David Kravitz

Teng Chiang Lin

Thomas J Meyer

Ajit Jain

Andy Wang

At least some instructions executed in a pipeline are each associated with corresponding trace information that characterizes execution of that instruction in the pipeline. A predetermined type of store instructions flow through a subset of contiguous stages of the pipeline. A signal is received to store a portion of the trace information. A stage before the subset of contiguous stages is stalled. A store instruction of the predetermined type is inserted into a stage at the beginning of the subset of contiguous stages to enable the store instruction to reach the memory access stage at which an operand of the store instruction including the portion of the trace information is sent out of the pipeline. The store instruction is filtered from a stage of the subset of contiguous stages that occurs earlier in the pipeline than a stage in which trace information is generated.

Managing trace information storage using pipeline instruction insertion and filtering

In some embodiments, an apparatus includes a transmission schedule module in at least one of a memory or a processing device that can select, at a first time, a data unit to send to a network device based at least in part on a value of a transmission rate counter indicating that the network is in a first state. The transmission schedule module can receive, at a second time, an indication of a number of buffers associated with the data unit and can calculate a size estimate of the data unit based on the number of buffers and a capacity associated with each buffer. The transmission schedule module can calculate at a third time, a temporary transmission rate count and can send a signal to transition the network device from the first state to a second state if the temporary transmission rate count meets a criterion.

Methods and apparatus for scheduling transmission of data in a network

One disclosed embodiment provides an integrated circuit that has a plurality of processors and a plurality of processor trace collection logic units. Each processor trace collection logic unit corresponds with, and is operatively coupled to, one of the processors. A separate filtering logic unit is operatively coupled to the plurality of processor trace collection logic units. In some embodiments of the integrated circuit, each processor trace collection logic unit is operative to continuously collect processor trace information from a corresponding operatively coupled processor. Each filtering logic unit is operative to monitor the continuous processor trace information for occurrence of a predetermined condition, and to store some of the processor trace information to memory in response to occurrence of that condition.

Apparatus and method for distributed instruction trace in a processor system

An apparatus for increasing scheduling efficiency in network devices may include (1) at least one memory device that stores at least one data chunk included in a packet, (2) a scheduler device that (a) schedules transmission of the packet that includes the data chunk and (b) issues a request to transmit the packet based at least in part on the scheduled transmission, and (3) a packet-delivery device that (a) receives the request to transmit the packet from the scheduler device, (b) prepares the packet for transmission at a faster rate than the scheduler device schedules the transmission of the packet, and then (c) facilitates transmitting the data chunk included in the packet to a computing device. Various other apparatuses, systems, and methods are also disclosed.

Apparatus, system, and method for increasing scheduling efficiency in network devices

A system includes processor cores that receive packets over a debug bus. The cores execute transactions in response to the packets. The packets are one of several types of packets such as a Second Access Bus (SAB) packet and Debug Access Bus (DAB) packet. The cores include specified resources and non-specified resources. A core that executes a transaction in response to a SAB packet accesses a non-specified resource and a core that executes a transaction in response to a DAB packet accesses a specified resources. A debug specification identifies the specified resources as being accessible by a debug controller. The debug specification does not identify the non-specified resources as being accessible by the debug controller.

Debug interface for multiple CPU cores

A network device may include an off-chip memory to store a free-list of buffer pointers. The network device may further include an on-chip controller that includes a prefetch buffer. The prefetch buffer may store unallocated buffer pointers that point to available memory locations in a different off-chip memory. The on-chip controller may receive an unallocated buffer pointer, determine, in response to receiving the unallocated buffer pointer, whether the prefetch buffer is full, store the unallocated buffer pointer in the prefetch buffer when the prefetch buffer is determined not to be full, and store the unallocated buffer pointer in the free-list, in the off-chip memory, when the prefetch buffer is determined to be full.

Growing community of inventors

Hopkinton, MA, United States of America

Gerald Lampert