Finisar Corporation

Gerald L Dybsetter

Jayne Catherine Hahin

Luke M Ekkizogloy

Lucy G Hosking

Stephen T Nelson

Timothy G Moran

Jason Y Miao

Daniel K Case

Lewis B Aronson

Greta Light

Georgios Kalogerakis

Ruldolf J Hofmeister

Curtis B Robinson, Jr

Luke M Ekkisogloy

Jayne C Hahain

The principles of the present invention relate to a multiply and divide circuit configured to interactively multiply and/or divide. The circuit may handle signed and unsigned values. The circuit comprises an instruction register configured to store a multiply or divide instruction, at one input register configured to store the multiply or divide operands, an Arithmetic Logic Unit ('ALU') configured to add provided values, and configuration circuitry. The configuration circuitry responds to the instructions and performs the multiply or divide operation by iteratively providing values to the ALU.

Integrated multiply and divide circuit

Chip identification pads for identification of integrated circuits in an assembly. In one example embodiment, an integrated circuit (IC) assembly includes a controller, a plurality of ICs, a shared communication bus connecting the controller to the plurality of ICs and configured to enable communication between the controller and each of the plurality of ICs, and a set of one or more chip identification pads formed on each IC. Each set of chip identification pads has an electrical connection pattern. The electrical connection pattern of each set is distinct from the electrical connection pattern on every other set. Each distinct electrical connection pattern represents a unique identifier of the corresponding IC thereby enabling the controller to distinguish between the ICs.

Chip identification pads for identification of integrated circuits in an assembly

An optical receiver comprising at least one processor and a memory including at least one of an encryption key or a decryption key and at least one of encryption microcode or decryption microcode that includes processor-executable instructions that, when executed by the at least one processor, cause the optical transceiver to perform the following: an act of performing an encryption or decryption operation on data received from a host computing system to thereby authenticate the optical transceiver.

Optical transceiver with vendor authentication

A mechanism for an optical transceiver to log information about its operational parameters to an off transceiver host computing system (hereinafter referred to simply as a 'host'). The optical transceiver may be communicatively coupled to the host. The optical transceiver is configured to identify operational information regarding itself. The operational information may include statistical data about operation, or may include measured parameters. The optical transceiver may log the information to the memory of the host in an off transceiver logging operation.

Optical transceiver with off-transceiver logging mechanism

Two or more optical transceivers coupled to each other by an optical link to optimize communication over the optical link. A first transceiver generates electrical data that represents an operational parameter for optimization. The transceiver then converts the electrical data into an optical signal and transmits the optical signal over the optical link to a second transceiver. The second transceiver recovers the electrical data from the optical signal and uses the recovered electrical data to change characteristics of the optical signal transmitted by the second transceiver.

Inter-transceiver module communication for optimization of link between transceivers

A two-wire interface in which upon determining that an operation is to be performed on a slave component, the master component monitors the data wire for a predetermined number of consecutive bits having a particular binary value. Upon detection such a sequence, the master component asserts a frame of a two-wire interface on the data wire. This detected predetermined number of consecutive bits will be considered to be the preamble. During at least some of the preamble phase, the master component is not asserting anything on the data wire. Instead, the data wire is pulled high (or low) by a weak pull-up (or pull-down) resistor. Furthermore, the frame is designed so that there are bits having a guaranteed binary value that is opposite what would be expected in the preamble, to thereby facilitate synchronization.

Two-wire interface in which a master component monitors the data line during the preamble generation phase for synchronization with one or more slave components

An optical transceiver configured to perform filtering of digital diagnostics prior to the filtered results being made accessible to a host computing system (hereinafter referred to simply as a 'host') that is communicatively coupled to the optical transceiver. The optical transceiver includes sensor(s) that measures analog operational parameter signals such as temperature and supply voltage. The analog signals are each converted to a plurality of digital samples by analog to digital converter(s). A processor executes microcode that causes the optical transceiver to perform filtering on the various samples. The optical transceiver may then make the filtered result accessible to the host.

Filtering digital diagnostics information in an optical transceiver prior to reporting to host

An operational optical transceiver configured to update operational firmware using an optical link of the transceiver. The optical transceiver includes at least one processor and a system memory capable of receiving firmware. The optical transceiver receives an optical signal over the optical link containing the update firmware. The optical transceiver then recovers the firmware from the optical signal. Finally, the optical transceiver provides to the system memory the recovered firmware, which when executed by the at least one processor alters the operation of the transceiver.

Inter-transceiver module communication for firmware upgrade

Systems and methods for an optical transceiver module to perform one or more diagnostic self-tests without the assistance of a host computing system. The optical transceiver module includes at least one processor, a persistent memory and a system memory. The persistent memory, which is coupled to the at least one processor, contains microcode. The microcode is loaded from the persistent memory to the system memory and executed by the at least one processor. The executed microcode causes the optical transceiver module to perform one or more diagnostic self-tests. The diagnostic result data of the one or more diagnostic self-tests is then stored in the persistent memory and is formatted for analysis. The formatted data may then be analyzed to ascertain the response of the optical transceiver to changes in its test environment.

Self-testing optical transceiver

An operational optical transceiver configured to self-validate a boot image loaded from the persistent memory early in the boot process. The optical transceiver includes a persistent memory, a controller, and a system memory. The controller initializes the boot process and begins to load information from the persistent memory to the system memory. Next, the controller detects early in the boot process boot image verification data in the information being sent to the system memory. The controller then determines if the boot image verification data has an expected value. If the verification data includes the expected value, the controller continues the boot process. If the verification data does not include the expected value, the controller will retry the boot process a predetermined number of times and will enter a default operational state if the expected value is not detected while retrying the boot process the predetermined number of times.

Early self-validation of persistent memory during boot in an optical transceiver

An optical transceiver (or optical transmitter or optical receiver) that includes a memory and a processor, which receives and executes custom microcode from a host computing system (hereinafter referred to simply as a 'host'). A user identifies desired optical transceiver operational features, each of which may be implemented using specific microcode. The memory receives custom microcode that aggregates all the specific microcode of the identified operational features from the host. The processor may later execute the custom microcode and cause the transceiver to perform the operational features.

Configuration of optical transceivers to perform custom features

A telecommunications system and constituent two-wire interface module. The two-wire interface module includes a first two-wire interface component configured to receive a first two-wire interface communication following a first two-wire interface protocol, and a second two-wire interface component configured to generate a second two-wire interface communication following a second two-wire interface protocol. The first and second two-wire interface communications each include a header portion and a payload portion. The second two-wire interface component is further configured to use one or more of the data fields from the payload portion of the first two-wire interface communication in the header portion of the second two-wire interface communication.

Use of a first two-wire interface communication to support the construction of a second two-wire interface communication

A mechanism that enables an optical transceiver to grant access to its memory on a per-segment basis. The optical transceiver includes a processor, system memory and a memory access table. The memory access table is comprised of access entries, each of which defines the access condition for a corresponding segment of memory. The processor reads the access entries for a particular segment of the memory. The processor or other optical transceiver component then determines whether or not to grant access to the memory segment based on the access entry read by the processor. Different levels of access control may be accommodated.

Multi-level memory access in an optical transceiver

A mechanism that enables an optical transceiver to configure memory on a per-segment basis. The optical transceiver includes a processing entity, system memory and a memory configuration table. The memory configuration table is comprised of configuration entries, each of which defines the configuration setting for a corresponding segment of memory. The processing entity reads the configuration entries for a particular segment of the memory. The processing entity then determines the set of one or more configuration settings for the memory segment based on the configuration entry read. This process may be repeated for multiple segments of memory.

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Scotts Valley, CA, United States of America

Gerald L Dybsetter