General Electric Company

Polaroid Corporation

Gerald J Michon

Dale M Brown

Jerome Johnson Tiemann

Hubert K Burke

Harold W Tomlinson

James William Kretchmer

Vikram Bidare Krishnamurthy

Glen William Brooksby

Dominic A Cusano

Steven L Garverick

Marvin Garfinkel

Thomas L Vogelsong

James R Toker

Louis Jacob Petrucco

Dale Marius Brown

Selim S Bencuya

A depletion mode MOSFET and resistor are fabricated as a silicon carbide (SiC) integrated circuit (IC). The SiC IC includes a first SiC layer doped to a first conductivity type and a second SiC layer overlaid on the first SiC layer and doped to a second conductivity type. The second SiC layer includes at least four more heavily doped regions of the second conductivity type, with two of such regions comprising MOSFET source and drain electrodes and two other of such regions comprising resistor electrodes. The second SiC layer includes an isolation trench between the MOSFET electrodes and the resistor electrodes. At least two electrically conductive contacts are provided as MOSFET electrode contacts, each being positioned over at least a portion of a respective MOSFET electrode and two other electrically conductive contacts are provided as resistor electrode contacts, each being positioned over at least a portion of a respective resistor electrode. An oxide layer extends over the second SiC layer with at least a portion of the oxide layer positioned between the MOSFET electrode contacts. A MOSFET gate electrode is positioned over the oxide layer, and coupling means are provided for electrically coupling one of the source, drain, and gate electrodes to one of the resistor electrodes.

Silicon carbide integrated circuits

A high temperature photocurrent detector circuit including a transimpedance amplifier having multiple stages of gain, and a driver amplifier which generates a driver current that is proportional to the photocurrent flowing through a photocurrent sensor. The voltage source utilizes source voltage wires to generate a supply current that is proportional to the driver current enabling the photocurrent detector circuit to operate as a two wire photocurrent detector circuit.

High temperature two-wire photocurrent detector circuit

A compact power circuit configured for circuit breaker applications includes, in one embodiment, a plurality of current transformers, each current transformer being coupled to a respective one of the phase lines of a power line to generate a current proportional to the current in the respective one of the phase lines. The circuit also includes a plurality of operational amplifiers, each of the operational amplifiers being coupled to a respective one of the current transformers. The operational amplifiers generate the phase signals v.sub.a, v.sub.b and v.sub.c respectively. A neutral phase signal Vn is generated by a current transformer coupled to the neutral phase line of the power line. A ground fault signal is generated from the vector sum of signals v.sub.a, v.sub.b, v.sub.c and V.sub.n.

Apparatus for determining load currents

A photocurrent detector circuit includes a photodiode coupled to an input terminal of a first operational amplifier. A first resistor has a first end coupled to the photodiode and a second end coupled to an output terminal of the first operational amplifier. A first diode has a first end coupled to the photodiode. A second resistor has a first end coupled to a second end of the first diode. A low gain bias network is coupled between a second end of the second resistor and the output terminal of the first operational amplifier. A second diode has a first end coupled to the photodiode. A clamp bias network is coupled between a second end of the second diode and the output terminal of the first operational amplifier. Preferably, the photodiode and the first and second diodes include silicon carbide. The detector may further include second and third operational amplifiers coupled to the output terminal of the first operational amplifier. A MOSFET differential pair can be coupled between the photodiode and the first operational amplifier to form a differential amplifier.

Photocurrent detector circuit with high sensitivity, fast response time,

Intensity of optical emission from a combustion flame within a gas turbine combustor is monitored through an optical window in the combustor wall by a primary detector. Because the window is susceptible to becoming coated with deposits during combustor operation, compensation for presence of a coating is achieved by directing illumination from an optical signal source, such as a silicon carbide light-emitting diode, into the window for internal reflection at an optical interface defined by the combustion side surface. A compensation detector, such as a silicon carbide photodiode, detects intensity of the internally reflected illumination as an indicator of the window coating thickness. The compensation detector is located at a non-combustion side of the window, along with a reference detector that responds to intensity of optical signal source illumination reflected from the non-combustion side surface of the window. An AC coupled differential synchronous detector circuit processes the compensation detector and reference detector output signals to compensate the primary detector output signals for the coating.

Flame sensor window coating compensation

A correlator for identifying global positioning satellites includes an antenna at a central location for receiving signature signals from a plurality of the satellites. Each received signal is converted from analog to digital form. A filter is employed to correlate each digital signal with a respective, unique code sequence. Each filtered digital signal is supplied to a circuit which produces an indication that identifies each satellite from the filtered digital signal supplied to the circuit.

Parallel correlator for global positioning system receiver

For protecting the gate insulating layer of an insulated gate field-effect transistor from electrostatic charges, the main terminals of a depletion mode (normally conducting) field-effect transistor, serving as a protection transistor, are connected between the gate and source terminals of the transistor to be protected, thus providing a shunt path for electrostatic charges when the protection transistor is not biased out of conduction. For normal operation, the protection transistor is biased out of conduction by applying to its gate terminal the voltage drop across a biasing resistor in series with the source terminal of the insulated gate field-effect transistor. This protection arrangement is particularly advantageous for silicon carbide field-effect transistors which are not readily suited to application of conventional (i.e. silicon transistor) gate insulating layer protection techniques.

Insulated gate transistor electrostatic charge protection

An optical detection system includes an array of photodetectors, each of which is positioned for receiving light and converting the light into an electrical signal. A plurality of high pass filters is positioned with each one of the high pass filters electrically coupled to a respective photodetector for passing a portion of a respective electrical signal having frequency components at least as high as the high pass filter cutoff frequency. In one embodiment, each one of the filters comprises a capacitance coupled to the photodetector and a depletion mode FET with shorted gate-to-source terminals coupled between the photodetector and a bias voltage source. Each of the FETs comprises a silicon substrate, a silicon dioxide first insulative layer having a trench and a first conductive layer covering a portion of the first insulative layer including a portion of the trench, and each of the capacitances comprises the first conductive layer, a second insulative layer covering a portion of the first conductive layer, and a second conductive layer covering a portion of the second insulative layer.

High temperature photodetector array

A depletion mode MOSFET and resistor are fabricated as a silicon carbide (SiC) integrated circuit (IC). The SiC IC includes a first SiC layer doped to a first conductivity type and a second SiC layer overlaid on the first SiC layer and doped to a second conductivity type. The second SiC layer includes at least four more heavily doped regions of the second conductivity type, with two of such regions comprising MOSFET source and drain electrodes and two other of such regions comprising resistor electrodes. The second SiC layer includes an isolation trench between the MOSFET electrodes and the resistor electrodes. At least two electrically conductive contacts are provided as MOSFET electrode contacts, each being positioned over at least a portion of a respective MOSFET electrode and two other electrically conductive contacts are provided as resistor electrode contacts, each being positioned over at least a portion of a respective resistor electrode. An oxide layer extends over the second SiC layer with at least a portion of the oxide layer positioned between the MOSFET electrode contacts. A MOSFET gate electrode is positioned over the oxide layer, and coupling means are provided for electrically couping one of the source, drain, and gate electrodes to one of the resistor electrodes.

Fabrication of silicon carbide integrated circuits

An output circuit for use with an array of high dynamic range analog sensor produces a digital output signal from the array prior to multiplexing, so as to avoid analog multiplexing noise. The analog signals are converted to digital form using a simple, parallel analog-to-digital conversion process at the outputs of low noise array amplifiers. By latching the converted digital output signals into shift registers, the analog multiplex function is obviated and the full dynamic range capability of the detector-amplifier combination is made available.

Digital interface circuit for high dynamic range analog sensors

An output circuit for use with an array of analog energy detectors includes a system for digital companding which is capable of providing output signals with an enhanced dynamic range. A digital compressor is provided for converting the output signals of the analog detectors into compressed digital values. Accumulators are provided for holding the output signals of the digital compressor. An expander is provided to expand the digital output signals held in the accumulators to determine the energy patterns impinging on the array of analog detectors.

Architecture for arbitrary nonlinear quantization of multi-channel data

An interferometer Fourier transform spectrometer, having increased speed, is capable of performing a Fourier transform in parallel, in analog form, using a weighted matrix. The spectrometer includes a linear detector array responsive to an interferogram. The detector array is coupled to a plurality of integrating sampling amplifiers. Each column of a group of columns of the matrix is coupled in parallel to a respective integrating sampling amplifier, and the output signals from each row of a group of rows form an output signal array.

High speed interferometer fourier transform spectrometer including a

In an array of charge injection device (CID) detectors, integer amplification is incorporated into each respective detector of the array. The amplifier for each CID detector in the array performs multiple nondestructive readouts. This provides a gain of N amplification of the signal charge in that detector wherein the signal charge is accurately replicated in a separate charge storage well defined by a magnitude capacitor coupled to the detector. Thus, at the end of the readout process, this separate well contains charge equal to N times the signal charge, N being the number of nondestructive readout cycles in the readout process.

Charge amplifier with precise, integer gain

An analog line store comprises a bank of storage capacitors n in number, an n:1 read multiplexer for sequentially sampling from the n storage capacitors as part of a read-then-write operation, a 1:n write multiplexer for sequentially sampling to the n storage capacitors as a further part of the read-then-write operation, and a scanning register for generating control signals for the write multiplexer and the read multiplexer. The storage capacitors have similar capacitances that are substantially invariant with change in stored charge. Such an analog line store is integrated together with a solid-state imager array to provide for the cancellation of fixed pattern noise from the imager video output signal.

Fixed-pattern noise correction circuitry for solid-state imager

A low capacitance radiation detector comprises a monocrystalline silicon substrate heavily doped to N type conductivity with a more lightly doped N type conductivity epitaxial layer formed on the substrate. A plurality of heavily doped N type upper surface layer segments are formed in the epitaxial layer. A patterned region of the epitaxial layer, heavily doped to P type conductivity and in the shape of parallel stripes joined at each end by a respective stripe perpendicular to the parallel stripes, is formed in the epitaxial layer and situated between adjacent ones of the upper surface layer segments, with each stripe extending into the epitaxial layer deeper than, and separated from, the upper surface layer segments so as to form a minority charge carrier-collecting PN junction with the epitaxial layer. The parallel stripes are spaced apart from each other by a distance smaller than or comparable to the minority charge carrier recombination diffusion length for the epitaxial layer, and the epitaxial layer thickness is smaller than or comparable to the minority charge carrier recombination diffusion length. In a second embodiment, the epitaxial layer has beveled edges and the heavily doped N type upper surface layer segments formed in the epitaxial layer extend over the beveled edges.

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Waterford, NY, United States of America

Gerald J Michon