Hewlett-packard Development Company, L.p.

Gerald Everett

Joe Bolding

Dan Tormey

Sachin Navin Chheda

Kent Andrew Dickey

A computer system that includes a controller that comprises a failure circuit and a management system is provided. The controller is configured to provide information to the management system at a first time, and the failure circuit is configured to cause the information to be provided to the management system at a second time in response to an acknowledgement from the management system not being receiving.

System and method for transferring information in a computer system

A method for testing the memory in a system with two or more processing units is provided that generally involves the following acts. The memory is divided into two or more sections&#x2014;one for each of the two or more processing units. Thus, each processing unit has an associated memory section. The memory is then checked with each memory section being checked with its associated processing unit. The act of checking the memory includes causing the address of a first encountered faulty location to be stored and causing a flag to be set in response to encountering a second faulty location. Finally, it is determined whether the flag has been set after the memory is checked. If so, a walk-through routine is then performed.

System and method for multi processor memory testing

A system and method for managing utilization in a stack. A stack base and a stack pointer are initialized for the stack. Upon fetching a program instruction to be executed in a computing environment, a determination is made if the program instruction involves accessing a location within a valid stack range that is defined by a high water mark operable to identify the stack pointer's farthest location from the stack base. The farthest location is indicative of how far the stack has grown at any time during the program's execution. A warning may be provided upon determining that the location to be accessed is not within the valid stack range.

Stack utilization management system and method for a single-stack arrangement

A system and method for synchronizing processors simulated in an architectural simulator for a multiprocessor environment. A synchronous breakpoint is set at a predetermined address location and a code portion targeted for execution on the target multiprocessor environment is launched on the simulator from a fixed location. Upon automatically stepping through a list of processors initialized in the simulator until each of the processors reaches the synchronous breakpoint, run control is returned to the user only after all processors have achieved a synchronous state. Debug operations may ensue thereafter by utilizing a debugger integrated with the architectural simulator.

Synchronous breakpoint system and method

A system and method for managing utilization in a unidirectional stack. An application programming interface (API) is provided for facilitating user interaction with a stack management system associated with a computing environment such as an architectural simulator. The unidirectional stack is initialized via the API with respect to a fixed stack marker boundary, a stack base and a stack pointer. A high water mark is maintained for tracking the stack pointer's farthest location from the stack base during the execution of a program. When a program instruction is operable to access a stack location, one or more validity rules are applied to determine if the access operation is permissible. Where the program instruction is operable to modify the stack pointer, another set of validity rules are applied to determine if the stack pointer operation is permissible. User warning and optional return of program control are available when an invalid access operation or stack pointer operation is attempted.

A system and method for managing stack utilization in a two-stack arrangement wherein the stacks are operable to grow towards each other. An application programming interface (API) is provided for facilitating user interaction with a stack management system associated with a computing environment such as an architectural simulator. Each of two stacks is initialized via the API with a stack base, a growth direction indicator and a stack pointer. High water marks are maintained for tracking each stack pointer's farthest location from the respective stack base during the execution of a program. When a program instruction is operable to access a location in either of the stacks, one or more validity rules are applied to determine if the access operation is permissible. Where the program instruction is operable to modify either of the stack pointers, another set of validity rules are applied to determine if the stack pointer operation is permissible. User warning and optional return of program control are available when an invalid access operation or stack pointer operation is attempted.

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Alta, CA, United States of America

Gerald Everett