Theseus Logic Inc.

Theseus Research, Inc.

Samsung Electronics Co., Ltd.

University of Minnesota

Gerald Edward Sobelman

Karl M Fant

David A Parker

Eui-seok Kim

Man-Ho Kim

Sang-woo Rhim

Daewook Kim

Dae-wook Kim

Beom-hak Lee

Jason J Hinze

Beam-hak Lee

Donovan L Raatz

David A Duncan

A method of modulating data, which is represented by two data types of 'high' and 'low', and demodulating the modulated data, is disclosed. In a method of data modulation and demodulation for a communication system which has a transmitting end modulating a data and a receiving end demodulating the transmitted data from the transmitting end, the data is represented by two types including &#x2018;high&#x2019; and &#x2018;low&#x2019;, and the receiving end receives at least one data which consists of at least one code-word spread by a unique orthogonal code. The receiving end adds up the received data in the unit of code-word, and subtracts the length of the orthogonal code from a value which is obtained by doubling the sum of the code-word, when the code-word of the orthogonal code is &#x2018;0&#x2019;. The receiving end then averages the result after the subtraction in the unit of orthogonal code length and extracts the result, and therefore, obtains the data from the transmitting end.

Method of data modulation and demodulation in SoC

A switching device of NoC (Networks on Chip) system and a scheduling method thereof. The switching device has a switching part having a plurality of input ports and a plurality of output ports, and a scheduler for setting a transmission route between the input ports and the output ports, determining the length of code based on the number of input ports having the data among the plurality of input ports, and assigning a predetermined code of the determined code length to the input port and the output port corresponding to the set transmission route. Because the code length is adjustably varied according to the number of transmission packets, switch performance improves.

Switching device of networks-on-chip system and scheduling method thereof

A NULL convention-threshold gate receives a plurality of inputs, each having an asserted state and a NULL state. The threshold gate switches its output to an asserted state when the number of asserted inputs exceeds a threshold number. The threshold gate switches its output to the NULL state only after all inputs have returned to NULL. Signal states may be implemented as distinct current levels.

Null convention threshold gate

A programmable gate array is disclosed for implementing asynchronous logic. In one embodiment, the array includes a set of cells, at least one of which includes a threshold gate having a plurality of inputs, an output, and a threshold value. Signals may assume an ASSERTED state having a logic meaning and a NULL state that has no logic meaning. The gate output switches to NULL when all inputs are NULL, and switches to the ASSERTED state when the number of ASSERTED inputs exceeds the threshold value. In the preferred embodiment, the gate exhibits hysteresis such that the output remains ASSERTED while the number of ASSERTED inputs remains greater than zero, less than the threshold value. In an alternate embodiment, an array of simplified threshold elements is used to form more complex threshold gates.

Programmable gate array

An m-of-n threshold gate is disclosed having an output stated derived from the voltage of a signal node. A &ldquo;Go-to-Data&rdquo; circuit pulls the signal node to a first state, corresponding to an ASSERTED (logically meaningful) output when a threshold number of inputs is in the ASSERTED state. A &ldquo;Go-to-NULL&rdquo; circuit pulls the signal node to a second state, corresponding to a NULL (logically meaningless) output when all inputs are in the NULL state. In a semi-dynamic embodiment, a weak feedback transistor holds the signal node in a predetermined state when some, but less than the threshold number of inputs is ASSERTED. In a dynamic embodiment, the signal node becomes isolated when less than the threshold number of inputs is ASSERTED, but holds sufficient charge to maintain the signal node in a state that existed at the time of isolation. A variety of GTN circuits are disclosed. Gates can be modified for the NULL state to be represented as ground (non-inverted) or other reference voltage (inverted). Alternating stages of inverted and non-inverted circuits can be used.

Semi-dynamic and dynamic threshold gates with modified pull-up structures

Threshold logic gates are disclosed that respond to signals that may assume at least a first state having an arithmetic or logic meaning, and a second NULL state that has no arithmetic or logic meaning. Threshold values may be equal to or less than the number of input signal lines. Threshold gates switch their outputs from NULL to a meaningful state when the threshold number of inputs assume meaningful states. Gates will hold outputs in a meaningful (or non-null) state when the number of asserted inputs remains positive, even if the number is less than the threshold. In one embodiment, threshold gates include a 'FLASH' input that forces the gate to NULL. In another embodiment, threshold gates include one or more 'SET' inputs that drive the gate output to NULL or to a meaningfull state.

Null convention logic gates with flash, set and reset capability

A programmable gate array is disclosed for implementing asynchronous logic. In one embodiment, the array includes a set of cells, at least one of which is programmed to function as a threshold gate having a plurality of inputs, an output, and a threshold value. Signals may assume a DATA state having a logic meaning and a NULL state that has no logic meaning. The gate output switches to NULL when all inputs are NULL, and switches to the ASSERTED state when the number of DATA inputs exceeds the threshold value. The gate preferably exhibit hysteresis such that the output remains DATA while the number of DATA inputs remains greater than zero, and less than the threshold value. In an alternate embodiment, and array of simplified threshold elements is used to form more complex threshold gates.

Look up table threshold gates

A programmable gate array is disclosed for implementing asynchronous logic. In one embodiment, the array includes a set of cells, at least one of which includes a threshold gate having a plurality of inputs, an output, and a threshold value. Signals may assume an ASSERTED state having a logic meaning and a NULL state that has no logic meaning. The gate output switches to NULL when all inputs are NULL, and switches to the ASSERTED state when the number of ASSERTED inputs exceeds the threshold value. In the preferred embodiment, the gate exhibits hysteresis such that the output remains ASSERTED while the number of ASSERTED inputs remains greater than zero, and less than the threshold value. In an alternate embodiment, an array of simplified threshold elements is used to form more complex threshold gates.

A NULL convention full adder receives a plurality of inputs, each having an asserted state and a NULL state. The adder switches its output to an asserted state when all inputs have been received and summed. The adder switches its output to the NULL state only after all inputs have returned to NULL. A register can be incorporated into each full adder. Multiple full adders are combined into multi-bit adders with registration.

Null convention adder

A NULL convention threshold gate receives a plurality of inputs, each having an asserted state and a NULL state. The threshold gate switches its output to an asserted state when the number of asserted inputs exceeds a threshold number. The threshold gate switches its output to the NULL state only after all inputs have returned to NULL.

A NULL convention threshold gate receives a plurality of inputs, each having an asserted state and a NULL state. The threshold gate switches its output to an asserted state when the number of asserted inputs exceeds a threshold number. The threshold gate switches its output to the NULL state only after all inputs have returned to NULL. Signal states may be implemented as distinct current levels.

Current mode null convention threshold gate

A digital signal processor including a digital FIR filter and memory for storing filter coefficients operates at a reduced power level by using array multipliers that calculate partial products only when the partial products in a preceding row of the array have stabilized. The dynamic CMOS adder arrays in each multiplier are triggered to perform their evaluations only after predetermined time periods have elapsed, which are sufficient to permit the preceding row to stabilize. Coefficients are addressed from the memory using low-power addressing circuits, such as a Gray code counter or a one-bit wide circular shift register, so that the overall digital signal processor consumes a reduced amount of power during memory addressing.

Growing community of inventors

Minnetonka, MN, United States of America

Gerald Edward Sobelman