Silicon Laboratories Inc.

Advanced Micro Devices Corporation

Gerald D Champagne

Terry Lee Dickey

Dana John Taipale

Brian Mirkin

David H Shen

Javier Elenes

G Tyson Tuttle

Safdar M Asghar

Péter Onódy

Mark A Ireton

Michael James Mills

John Allen

William W K Tang

Christopher S Gregg

David Mervine

Corbett A Marler

A circuit includes a controller configured to determine a calibration state of a circuit, to determine an active mode state of the circuit, and to select a type of calibration operation based on the calibration state. The controller is configured to control timing of the selected type of calibration operation in response to determining the calibration state to correspond to a time when the circuit is not active.

Apparatus and method of background temperature calibration

A method includes estimating a temperature change to an integrated circuit, which is associated with a pending transmission from the integrated circuit. The method includes, based on the estimated temperature change, regulating at least one parameter that is associated with the pending transmission to maintain a temperature of the integrated circuit below a temperature threshold.

Transmission-based temperature control for an electrical device

A circuit includes a temperature sensor configured to determine a circuit temperature and includes an analog circuit including one or more controllable circuit elements. The analog circuit includes at least one adjustable parameter. The circuit further includes a controller coupled to the temperature sensor and configured to select a threshold temperature. The controller is configured to control the analog circuit in response to the circuit temperature to selectively adjust at least one adjustable parameter of the analog circuit when the temperature exceeds the selected threshold temperature.

Apparatus and method of adjusting analog parameters for extended temperature operation

A radio frequency (RF) receiver comprises an analog receiver, a digital signal processor, a clock synthesizer, and a microcontroller. The analog receiver has an input for receiving an RF input signal, and an output for providing a digital intermediate frequency (IF) signal. The digital signal processor has a first input for receiving the digital IF signal, a second input for receiving a clock signal, and a signal output for providing an IF output signal. The clock synthesizer has an input for receiving a clock control signal, and an output for providing the clock signal. The a microcontroller has an input for receiving a channel selection signal, wherein the microcontroller provides the clock control signal to control a frequency of the clock signal dynamically in response to a channel selection input to place a sub-harmonic at a tolerable frequency of a selected channel.

Radio frequency (RF) receiver with dynamic frequency planning and method therefor

A method and apparatus for determining an RC (resistive-capacitive) time constant is disclosed. In one embodiment, a method comprises determining a first period of oscillation when an oscillator is operating in a first configuration. The method further comprises determining a second period of oscillation when the oscillator is operating in a second configuration. A measurement circuit is configured to determine a resistive-capacitive (RC) time constant of the oscillator by determining a mean of the first and second periods.

RC calibration using chopping

A radio frequency (RF) receiver comprises an analog receiver, a digital processor, a clock synthesizer, and a microcontroller. The analog receiver has an input for receiving an RF input signal, and an output for providing a digital intermediate frequency (IF) signal. The digital signal processor has a first input for receiving the digital IF signal, a second input for receiving a clock signal, and a signal output for providing an IF output signal. The clock synthesizer has an input for receiving a clock control signal, and an output for providing the clock signal. The a microcontroller has an input for receiving a channel selection signal, wherein the microcontroller provides the clock control signal to control a frequency of the clock signal dynamically in response to a channel selection input to reduce interference of sub-harmonics created by the clock signal on the analog receiver.

Methods and systems for blending the audio output from a received FM signal between stereo and mono in which the L&#x2212;R (left-minus-right) gain of the FM MPX may be adjusted as a function of RF signal to noise ratio (SNR) and the L+R (left-plus-right) noise level. During blending, the L&#x2212;R gain based on the RF SNR and L+R noise may be reduced in a manner such that the total noise is kept substantially constant throughout the stereo-to-mono blend region.

Methods and systems for blending between stereo and mono in a FM receiver

A radio frequency (RF) receiver comprises an analog receiver, a digital processor, and a clock synthesizer. The analog receiver has an input for receiving an RF input signal, and an output for providing a digital intermediate frequency (IF) signal. The digital processor has a first input for receiving the digital IF signal, a second input for receiving a clock signal, a signal output for providing an IF output signal, and a control output for providing a clock control signal. The clock synthesizer has an input for receiving the clock control signal, and an output for providing the clock signal. The digital processor controls a frequency of the clock signal dynamically in response to a channel selection input to reduce interference of sub-harmonics created by the digital processor on the analog receiver.

A method is provided that contemplates including filtered decode values in an RDS/RBDS output signal. The filtered decode values are generated from reliable values. The reliable values are generated from corresponding received values from each of at least two groups of RDS/RBDS data in an RDS/RBDS input signal. The method also comprises preventing an error correction code (ECC) unit from modifying the filtered decode values in the RDS/RBDS output signal.

RDS/RBDS decoder with reliable values

A receiver including first circuitry configured to combine corresponding soft decision values from at least two groups of RDS/RBDS data transmitted as part of a broadcast channel to generate a set of combined values and second circuitry configured to identify a subset of the combined values that indicate a relatively constant subset of the received values from the at least two groups of the RDS/RBDS data is provided.

System and method for transmitting RDS/RBDS data

Decoder with soft decision combining

A frequency modulation (FM) radio receiver includes a processing unit that may generate a magnitude value corresponding to a signal strength of each of a plurality of digital samples of a received FM signal. The receiver also includes a noise estimation unit that may filter the magnitude values using a high pass filter and may generate a noise value representative of a noise portion of the received FM signal based upon the filtered magnitude values.

Frequency modulation radio receiver including a noise estimation unit

A method of communicating via an electronic mail system includes creating a text portion of a message. An audio portion of the message is also recorded. The audio portion is digitized. The digitized audio portion is coupled to the text portion to form a complete message. The complete message is transmitted via the electronic mail system. The complete message is received at a destination unit, which provides for the visual displaying of the text portion of the message, together with the audio outputting of the audio portion of the message.

Digitized audio data attachment to text message for electronic mail

A system and method for performing software patches for embedded system devices in which the firmware of the system is included in non-alterable storage of the device. The patch mechanism provides a means for finding firmware errors, prototyping fixes to the errors and/or prototyping new functionality of the firmware of the embedded system. The system comprises an embedded system device coupled to an external memory. The device includes a non-alterable memory, including firmware, coupled to a processor. The device further includes a relatively small amount of patch RAM within the device also coupled to the processor. The patches are loaded from the external memory into the patch RAM. The device further includes a means for determining if one or more patches are to be applied. If the device detects a patch to be applied, the system loads the patch from the external memory into the patch RAM. The device also includes a breakpoint register. When the value of the program counter of the processor equals the value in the breakpoint register, a patch insertion occurs, i.e., the processor deviates from executing firmware to executing patch instructions. Preferably, the embedded system device comprises a single integrated circuit. The processor may include a plurality of breakpoint registers. The patch may be encrypted for increased security. Multiple patches may be chained together, and run-time patch replacement is contemplated.

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Buda, TX, United States of America

Gerald D Champagne