Verigy (Singapore) Pte. Ltd.

Advantest (Singapore) Pte Ltd

Adv Antest Corporation

Inovys Corporation

Gerald Chan

Richard C Dokken

Alfred Larry Crouch

Mei-Mei Su

Eric Kushnick

Phillip D Burlison

John C Potter

Takehiko Ishii

Jacob Joseph Orbon, Jr

Andrew Niemic

Automated test equipment (ATE) capable of performing a test of semiconductor devices is presented. The ATE comprises a computer system comprising a system controller communicatively coupled to a tester processor. The system controller is operable to transmit instructions to the processor and the processor is operable to generate commands and data from the instructions for coordinating testing of a plurality of devices under test (DUTs). The ATE further comprises a plurality of FPGA components communicatively coupled to the processor via a bus. Each of the FPGA components comprises at least one hardware accelerator circuit operable to internally generate commands and data transparently from the processor for testing one of the DUTs. Additionally, the tester processor is configured to operate in one of several functional modes, wherein the functional modes are configured to allocate functionality for generating commands and data between the processor and the FPGA components.

Test architecture having multiple FPGA based hardware accelerator blocks for testing multiple DUTs independently

A process for improving design-limited yield by collecting test fail data, converting to electrical faults, and localizing to physical area on semiconductor die. The steps of identifying an area on a wafer containing a fault to enable the analysis of specific defects, accumulating data suitable for yield monitoring analysis based on pattern test failures logged on scan cells in scan chains on automatic test equipment, and translating scan cell and scan chain failure reports to geometric locations of electrical structures on wafers.

Process for improving design-limited yield by localizing potential faults from production test data

A process for conserving storage space and time while recording not only a pass or fail result per die but also additional failure test pattern data by computing and comparing digital fault signatures or hash values on a tester.

Process for improving design limited yield by efficiently capturing and storing production test data for analysis using checksums, hash values, or digital fault signatures

A method for operating a secure semiconductor IP access server to support failure analysis. A client presents a test failure and failure type to an automated server which traverses an electronic product design, definition, and test database to report specifically those components and interconnect likely to cause the failure with geometrical information which may be displayed on the client. Other aspects of semiconductor IP are protected by the server by limiting the trace mechanism and renaming components.

Method for operating a secure semiconductor IP server to support failure analysis

A method for data logging from inside a semiconductor device, yielding timing performance information about the logic behind each and every flip-flop in the scan chain and displaying the sensitivity of certain flipflops to speed related manufacturing defects. The method comprises steps for testing, measuring, storing, and analyzing records for frequency characterization of complex digital semiconductors.

System and method for device performance characterization in physical and logical domains with AC SCAN testing

A process for identifying the location of a break in a scan chain in real time as fail data is collected from a tester. Processing a test pattern before applying it on a tester provides a signature enabling a method for a tester to identify a scan cell which is stuck during the time the tester is operating on a device under test rather than accumulating voluminous test data sets for delayed offline analysis.

Growing community of inventors

Saratoga, CA, United States of America

Gerald Chan