Analog Devices,inc.

Analog Deivces, Incorporated

Gerald A Miller

Michael C W Coln

Andrew M Mallinson

John W Fernandes

Stephen R Lewis

Bruce E Amazeen

Christopher S O'Connor

Scott H Wayne

Mick Mueck

Methods and apparatus for jitter and load insensitive charge transfer are disclosed. A quantity of charge is transferred to or from a load during a transfer interval, wherein the charge transferred is significantly insensitive to load characteristics and variations in the transfer interval. A succession of identical or different quantities of charge may be transferred to or from the load during successive transfer intervals. The charge transfer circuit may be employed in mixed switched/continuous-time circuit configurations, and in particular may be used as a unipolar or bipolar one-bit digital-to-analog converter to provide quantized feedback in a sigma-delta analog-to-digital converter circuit configuration. The charge transfer circuit avoids problems of integrating amplifier nonlinearity and input signal distortion in such sigma-delta analog-to-digital converter circuits, and facilitates monolithic fabrication of sigma-delta analog-to-digital converters using standard integrated circuit fabrication techniques.

Jitter and load insensitive charge transfer

A multi-stage, low-offset, fast-recovery, comparator system and method for: reducing the input offset voltage of the zeroing amplifier by a factor essentially equal to gain of the zeroing amplifier; reducing the input offset voltage of the combined main and zeroing amplifiers by a factor essentially equal to the product of the gains of the main and zeroing amplifiers; and amplifying the input signal to the amplification stage in accordance with the gain of the main amplifier to generate an amplified high-resolution signal.

Multi-stage, low-offset, fast-recovery, comparator system and method

An auto-zeroing sample-hold amplifier capable of tracking an input voltage and, when designated, sampling and accurately holding an input voltage with no gain or offset errors includes input and output buffers with complementary, equal-magnitude offsets for minimizing offset voltage errors. An input voltage is sampled across a primary hold capacitor as well as a secondary hold capacitor [at the amplifier output to] in a sample mode. In a hold mode, the capacitors, in conjunction with the buffers and a transconductance amplifier, form a negative feedback loop around the transconductance amplifier to hold the sampled voltage and reduced voltage excursions at the output of the sample-hold amplifier. A special cancellation switch and capacitor are included for differentially cancelling voltage errors caused by switch charge feed-through onto the primary hold capacitor.

Sample-hold amplifier circuit

A sample/hold amplifier comprising two transconductance stages with their inverting input terminals connected together. In sample mode, the input signal is connected to the non-inverting input of the first stage, and a hold capacitor is connected to the non-inverting input terminal of the second stage and driven by the amplifier output through a feedback circuit which forces the hold capacitor voltage to track the input signal. Upon switchover to hold mold, the roles of the two transconductance stages are interchanged: The non-inverting input terminal of the first stage is connected through a feedback circuit to the amplifier output, and the second stage receives as an input signal the voltage of the hold capacitor, which now is disconnected from the amplifier output. The net offset voltage developed on the hold capacitor is the difference between the respective offsets of the two transconductance stages. This net offset voltage is compensated for by an equal and opposite voltage in hold mode, due to the interchange of roles of the two transconductance stages.

Sample/hold amplifier for integrated circuits

A 12-bit sub-ranging A/D converter which operates through four successive sub-ranging cycles with an 8:1 gain change between the cycles. The residue signal for each cycle is directed to a four-bit flash converter the output of which sets the latches for corresponding bit-current-sources of a DAC. The flash converter input circuit comprises identical residue and reference amplifiers driving symmetrical residue and reference networks for controlling the flash converter comparators. The DAC output for each cycle is compared with the analog input signal to produce a corresponding new residue signal. There are 15 bit-current-sources, three for the first cycle, and four for each of the last three cycles. The MSB of each group of four bit-current sources is an overlap bit having the same current weighting as the LSB of the preceding group. Setting of the overlap bit makes it possible to develop a correct output for the DAC for each of the 2nd through 4th cycles without altering bits already determined in previous cycles. The converter provides an optional 5th cycle making possible a 14-bit output or an increased yield of 12-bit converters.

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Hudson, NH, United States of America

Gerald A Miller