Realtek Semiconductor Inc.

Knights Technology, Inc.

Icube Corp.

Ger-Chih Chou

Chun-chi Yu

Chih-Wei Chang

Chih-wei Chang

Li-Jun Gu

Fu-chin Tsai

Tsen-Shau Yang

Fu-Chieh Hsu

Chun-Chi Yu

Wen-Jai Hsieh

Fu-Chin Tsai

Kuo-Wei Chi

Kent Blair Dahlgren

Min-Han Tsai

Kuang-Hua Ken Huang

Christopher Yih

The present disclosure discloses a memory access interface device. A clock generation circuit generates reference signals. A transmitter transmits an output command and address signal to a memory device according to the reference signals. A signal training circuit executes a training process in a training mode that includes steps outlined below. A training signal is generated such that the training signal is transmitted as the output command and address signal. The training signal and the data signal generated by the memory device are compared to generate a comparison result indicating whether the data signal matches the training signal. The comparison result is stored. The clock generation circuit is controlled to modify a phase of at least one of the reference signals to be one of a plurality of under-test phases to execute a new loop of the training process until all the under-test phases are trained.

Memory system, memory access interface device and operation method thereof

The present disclosure discloses a memory access interface device. A clock generation circuit generates reference clock signals. Each of access signal transmission circuits each includes a duty cycle adjusting circuit, a duty cycle detection circuit, a frequency division circuit and an asynchronous first-in-first-out circuit. The duty cycle adjusting circuit performs duty cycle adjustment on one of the reference clock signals according to a duty cycle detection signal to generate an output clock signal having a duty cycle. The duty cycle detection circuit detects a variation of the duty cycle to generate the duty cycle detection signal. The frequency division circuit divides a frequency of the output clock signal to generate a read clock signal. The asynchronous first-in-first-out circuit receives an access signal from a memory access controller and outputs an output access signal according to the read clock signal to access the memory device accordingly.

Memory system and memory access interface device thereof for supporting different speed modes

Disclosed is a DDR SDRAM signal calibration device capable of adapting to the variation of voltage and/or temperature. The device includes: an enablement signal setting circuit configured to generate data strobe (DQS) enablement setting; a signal gating circuit configured to generate a DQS enablement setting signal and a DQS enablement signal according to the DQS enablement setting and then output a gated DQS signal according to the DQS enablement signal and a DQS signal; and a calibration circuit configured to generate a first delay signal according to the DQS enablement setting signal and generate a second delay signal according to the first delay signal, the calibration circuit further configured to generate a calibration signal according to the first and second delay signals and the DQS signal. The enablement signal setting circuit maintains or adjusts the DQS enablement setting according to the calibration signal.

DDR SDRAM signal calibration device and method

The present disclosure discloses a memory access interface device. A data processing circuit receives a data signal including 2M pieces of data from a memory device. A sampling clock generation circuit receives a data strobe signal from the memory device to generate a valid data strobe signal having P valid strobe pulses and further generate a sampling clock signal accordingly, in which P is larger than M. A sampling circuit samples the data signal according to the sampling clock signal to generate sampling results. A control circuit determines valid sampling results according to a time difference between the valid data strobe signal and the data signal and outputs valid data generated according to the valid sampling results as a read data signal to a memory access controller.

Memory system and memory access interface device thereof

A double data rate synchronous dynamic random access memory includes a control circuit and an output driving circuit. The control circuit provides a first voltage, a second voltage, a third voltage and a fourth voltage. The output driving circuit couples to the control circuit and includes a pull-up circuit, a pad and a pull-down circuit. When a voltage of the pad rises from the fourth voltage to the first voltage, a voltage between a drain and a source of a second driving transistor in the pull-down circuit is between the third voltage and the fourth voltage. When a voltage of the pad falls from the first voltage to the fourth voltage, a voltage between a drain and a source of a first driving transistor in the pull-up circuit is between the first voltage and the second voltage.

Double data rate synchronous dynamic random access memory and output driving circuit thereof

A local area network switch includes a set of input ports each receiving and storing incoming packets from a corresponding network station, a set of output ports each forwarding packets to a corresponding network station, and a switching system for routing packets from the input ports to the output ports. The output ports are interconnected to form an output token passing ring and the input ports are interconnected to form an input token passing ring. Whenever an idle output port receives the output token, it holds the output token and signals the input ports to start an input token passing cycle. During an input token passing cycle, an input port storing a packet destined for an output token holder terminates the input token passing cycle when it receives the input token and signals the switching system to establish a connection to the output token holder. To fairly distribute arbitration priority, input and output ports starting positions are rotated for successive input and output token passing cycles.

Network switch with arbitration sytem

A system for testing integrated circuits is disclosed which uses a mechanical microprobe and the integrated circuit's CAD database. The system is integrated with the CAD database in such a manner that after an initial alignment operation between the CAD database and the integrated circuit being tested, the microprobe can be moved automatically to any spot on the circuit by choosing a point in the CAD database and placing a cursor on that spot. The microprobe is then automatically moved to the point so indicated. A contact sensing circuit allows the probe to be driven into the actual circuit to take measurements or inject test signals without fear of damaging the integrated circuit. The system can operate in numerous modes, each of which provide a different way of visualizing the circuit being tested.

CAD driven microprobe integrated circuit tester

A technique for detecting whether electrical contact between a probe tip and a device under test ('DUT') has been established. A contact sensing circuit has a ground that is isolated from the ground of the DUT (and remaining portions of the test equipment) during contact sensing. The contact sensing circuit has elements that operate to apply a characteristic signal to one of the DUT terminals, such as its ground terminal. This causes virtually all the DUT circuit traces to track the applied signal (relative to the contact sensing ground). The contact sensing circuit further includes elements, coupled to the probe, that operate to detect the presence of the characteristic signal (relative to the contact sensing ground) on the probe. Once electrical contact has been established, the characteristic signal output is disconnected from the DUT, the test equipment ground is connected to the contact sensing circuit ground, and the probe output is coupled to the relevant portions of the test equipment circuitry.

Growing community of inventors

San Jose, CA, United States of America

Ger-Chih Chou