Neomagic Israel Ltd.

Faust Communications Holdings, LLC

Georgiy Shenderovich

Memory apparatus including a byte-bank organized in N rows and 8 columns, having a capacity of log(N) bytes, a log(N) bit address bus operative to address the byte-bank, an address offset bus operative to generate offsets (e.g., one-bit offsets) to bits of the byte-bank with an address conversion operator, and an adder in operative communication with the address offset bus and the log(N) bit address bus, the adder operative to add addresses of the byte-bank with the offset generated by the address conversion operator and output a result to the log(N) bit address. A random access memory array may include a plurality of the byte-banks.

Nonaligned access to random access memory

A method for bus arbitration comprising assigning priorities changeable with time to requesters of a data bus, and for simultaneous bus requests by more than one requestor, granting usage of the bus to the requester with the highest priority at the time of the bus requests.

Growing community of inventors

Petah-Tiqwa, Israel

Georgiy Shenderovich