Intel Corporation

Skyworks Solutions, Inc.

Apple Inc.

Georgios Yorgos Palaskas

Ashoke Ravi

Stefano Pellerano

Paolo Madoglio

Ofir Degani

Rotem Banin

Hasnain Lakdawala

Marian K Verhelst

Zdravko Boos

Bernd-Ulrich Klepser

Hongtao Xu

Shilpa Talwar

Kameran Azadet

Hosein Nikopour

Bryan K Casper

Wook Bong Lee

Michael Genossar

Claudio Da Silva

Debabani Choudhury

Aleksey A Lyalin

Sidharth Dalmia

Albert Molina

Igal Kushnir

Duncan Kitchin

Saku Lahti

Oner Orhan

Shayan Farahvash

Emanuel Cohen

Gadi Shor

Mikko S Komulainen

Jayprakash Thakur

Eren Sasoglu

Arnaud Lucres Amadjikpe

Kunal Datta

Menashe Soffer

Ana M Yepes

Moshe Teplitsky

Run Levinger

Omer Asaf

Chintan S Thakkar

Eshel Gordon

Nebil Tanzi

Josef Hagn

Erkan Alpman

Ron Pongratz

Tawfiq Musah

Baljit Singh

Peter Sagazio

Eyal Goldberger

Amit Freiman

Shuhei Yamada

Kaushik Dasgupta

Eran Gerson

Yossi Tsfati

Shmuel Ravid

Anandaroop Chakrabarti

Meir Gordon

Resti Montoya Moreno

Noam Kogan

Nir Weisman

Naftali Landsberg

Ra'anan Sover

Mikko M Lampinen

Huiming Xu

Miroslav Baryakh

Avi Tsarfati

Lior Shakedd

Anat Bazov

Stefano Brenna

Saeid Daneshgar Asl

Amr M Fahim

Shinwon Kang

Te Yu Kao

Nathan G Narevsky

Stewart S Taylor

Krishnamurthy Soumyanath

Richard B Nicholls

Peter Preyler

Gregory Chance

Telesphor Kamgaing

Valluri Ramana Rao

Andreas Menkhoff

Rajarshi Mukhopadhyay

Keith A Holt

Gregory W Chance

Brandon R Davis

Stanley K Ling

Sebastian Sievert

Soumyanath Krishnamurthy

Dirk Friedrich

Milad Darvishi

Kailash Chandrashekar

Michael Bruennert

Parmoon Seddighrad

Jeyanandh K Paramesh

Sunghyun Park

Andreas Boehme

Stefan H Andersson

Ian A Rippke

Jorge Hermosillo

Millimeter wave (mmWave) technology, apparatuses, and methods that relate to transceivers, receivers, and antenna structures for wireless communications are described. The various aspects include co-located millimeter wave (mmWave) and near-field communication (NFC) antennas, scalable phased array radio transceiver architecture (SPARTA), phased array distributed communication system with MIMO support and phase noise synchronization over a single coax cable, communicating RF signals over cable (RFoC) in a distributed phased array communication system, clock noise leakage reduction, IF-to-RF companion chip for backwards and forwards compatibility and modularity, on-package matching networks, 5G scalable receiver (Rx) architecture, among others.

Wireless communication technology, apparatuses, and methods

An electronic device may include wireless circuitry having digital-to-analog converters, filters, mixers, and current buffers disposed between the filters and the mixers. The current buffers may provide proper resistance termination for the filters. The current buffers may include current mirrors formed from diode-connected n-type transistors and diode-connected p-type transistors, which collectively provide a linear input resistance. The current mirrors may receive a high voltage from a voltage regulator having a replica current mirror and proportional-to-absolute-temperature current sources.

Electronic devices having complementary current mirror circuitry

Power amplifiers with adaptive bias for envelope tracking applications are provided herein. In certain embodiments, an envelope tracking system includes a power amplifier that amplifies a radio frequency (RF) signal and that receives power from a power amplifier supply voltage, and an envelope tracker that controls a voltage level of the power amplifier supply voltage based on an envelope of the RF signal. The power amplifier includes a current mirror having an input that receives a reference current, an output electrically connected to the power amplifier supply voltage, and a node that outputs a gate bias voltage. The power amplifier further includes a field-effect transistor that amplifies the radio frequency signal and a first depletion-mode transistor having a gate connected to the node of the current mirror and a source connected to a gate of the field-effect transistor.

Power amplifiers with adaptive bias for envelope tracking applications

Power amplifiers with adaptive bias for envelope tracking applications are provided herein. In certain embodiments, an envelope tracking system includes a power amplifier that amplifies a radio frequency (RF) signal and that receives power from a power amplifier supply voltage, and an envelope tracker that generates the power amplifier supply voltage based on an envelope of the RF signal. The power amplifier includes a field-effect transistor (FET) for amplifying the RF signal, and a current mirror including an input that receives a reference current and an output connected to the power amplifier supply voltage. An internal voltage of the current mirror is used to bias the gate of the FET to compensate the FET for changes in the power amplifier supply voltage arising from envelope tracking.

Modulation circuitry is configured to generate a phase modulated signal having an output frequency that corresponds to a local oscillator (LO) signal divided by N.5. A phase locked loop (PLL) is configured to generate an LO signal having a frequency that is N.5 times the output frequency. Pulse circuitry configured to generate, based at least on a value of N, an edge signal including a pulse aligned with a positive edge of the LO signal and a pulse aligned with a negative edge of the LO signal. The edge signal is used to generate the phase modulated signal.

Modulation circuitry with N.5 division

An apparatus for interpolating between a first and a second signal is provided. The apparatus includes a plurality of interpolation cells coupled to a common node of the apparatus. Further, the apparatus includes a control circuit configured to supply, based on a control word, respective selection signals to each of the plurality of interpolation cells. At least one of the plurality of interpolation cells is configured to couple the common node to a first potential if the first signal and the second signal are both at a first signal level, couple the common node to a second potential, which is different from the first potential, if the first signal and the second signal are both at a second signal level, which is different from the first signal level, and to decouple the common node from at least one of the first potential and the second potential if the first signal and the second signal are at different signal levels. Additionally, the at least one of the plurality of interpolation cells is configured to switch, based on a state indicated by the respective selection signal, to coupling the common node to the second potential in response to a transition of either the leading one or the trailing one of the first signal and the second signal from the first signal level to the second signal level.

Apparatus and method for interpolating between a first and a second signal

This application discusses, among other things, apparatus and methods for sharing a local oscillator between multiple wireless devices. In certain examples, an apparatus can include a central frequency synthesizer configured to provide a central oscillator signal having a first frequency, a first transmitter, the first transmitter including a first transmit digital-to-time converter (DTC) configured to receive the central oscillator signal and to provide a first transmitter signal having a second frequency, and a first receiver, the first receiver including a first receive DTC configured to receive the central oscillator signal and to provide a first receiver signal having a first receive frequency.

Direct digital frequency generation using time and amplitude

A digital to time converter (DTC). The DTC includes a lookup table, a divider, a thermometric array and a switched capacitor array. The lookup table is configured to generate one or more corrections based on thermometric bits of an input signal. The divider is configured to generate a plurality of divider signals from an oscillator signal based on the one or more corrections. The thermometric array is configured to generate a medium approximation signal from the plurality of divider signals based on the one or more corrections. The switched capacitor array is configured to generate a digital delay signal from the medium approximation signal based on the one or more corrections and switched capacitor bits of the input signal.

Digital time converter systems and methods

This document discusses apparatus and methods for reducing energy consumption of digital-to-time converter (DTC) based transmitters. In an example, a wireless device can include a digital-to-time converter (DTC) configured to receive phase information from a baseband processor and to provide a first modulation signal for generating a wireless signal, and a detector configured to detect an operating condition of the wireless device and to adjust a parameter of the DTC in response to a change in the operating condition.

Power saving technique for digital to time converters

Apparatus and methods for disrupting or preventing periodicity in DTC circuits are provided. In an example, a communication circuit can include a digital-to-time converter (DTC) and a processing path coupled to the DTC. The DTC can be configured to receive reference information, modulation information and first dither information, and to provide a modulated signal using the reference information, the modulation information and the first dither information. The processing path can be configured to receive second dither information and to cancel the first dither information using the second dither information, wherein the DTC is configured to disrupt processing periodicity of the communication circuit using the first dither information.

Apparatus and method for digital-to-time converter spur dithering

An apparatus includes a die with through-silicon vias and radio frequency integrated circuit capabilities and it is vertically integrated with a phased-array antenna substrate. The through-silicon via and a radio frequency integrated circuit is coupled to a plurality of antenna elements disposed on the phased-array antenna substrate where each of the plurality of antenna elements is coupled to the through-silicon vias and radio frequency integrated circuit through a plurality of through-silicon vias. A process of assembling the through-silicon vias and radio frequency integrated circuit to the phased-array antenna substrate includes testing the apparatus.

Chip packages including through-silicon via dice with vertically inegrated phased-array antennas and low-frequency and power delivery substrates

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Portland, OR, United States of America

Georgios Yorgos Palaskas