Koninklijke Philips Corporation N.V.

Georgios Petkos

Steven Thomas Peake

Raymond J Grover

Philip Rutter

Christopher Martin Rogers

Robert J Farr

Peter J Forbes

A device termination structure, and/or a gate bus-bar structure, and/or other end structure is provided for at least one group of cells in a cellular trench-gate semiconductor device, for example a power MOSFET. In this end structure, a conductive layer (), for example of polysilicon gate material, extends on an intermediate insulating layer () over a higher-doped (P+) end region () of the channel-accommodating region (). This insulating layer () comprises an area () of a trench-etch mask (), preferably comprising silicon nitride, that is of greater thickness than the gate dielectric layer (). A window () extends through the trench-etch mask () at a location where an end trench () extends into the P+ region (). The end trench () is an extension of the insulated gate trench () into the P+ region () and accommodates an extension () of the trench-gate (). The conductive layer () is connected to the trench-gate extension () via the window (). The lateral extent of the conductive layer () terminates in an edge () that is defined on the trench-etch mask ().

Method for manufacturing trench gate semiconductor device

A device termination structure, and/or a gate bus-bar structure, and/or other end structure is provided for at least one group of cells in a cellular trench-gate semiconductor device, for example a power MOSFET. In this end structure, a conductive layer ( ), for example of polysilicon gate material, extends on an intermediate insulating layer ( ) over a higher-doped (P&plus;) end region ( ) of the channel-accommodating region ( ). This insulating layer ( ) comprises an area ( ) of a trench-etch mask ( ), preferably comprising silicon nitride, that is of greater thickness than the gate dielectric layer ( ). A window ( ) extends through the trench-etch mask ( ) at a location where an end trench ( ) extends into the P&plus; region ( ). The end trench ( ) is an extension of the insulated gate trench ( ) into the P&plus; region ( ) and accommodates an extension ( ) of the trench-gate ( ). The conductive layer ( ) is connected to the trench-gate extension ( ) via the window ( ). The lateral extent of the conductive layer ( ) terminates in an edge ( ) that is defined on the trench-etch mask ( ).

Trench-gate semiconductor devices and their manufacture

Compact trench-gate semiconductor devices, for example a cellular power MOSFET with sub-micron pitch (Yc), are manufactured with self-aligned techniques that use sidewall spacers ( ) in different ways. Thereby, the source region ( ) and a contact window ( ) for a source electrode ( ) can be self-aligned to a narrow trench ( ) containing the trench-gate ( ). Thereby, the channel-accommodating region ( ) can also be provided after forming the trench-gate ( ), and with very good control of its doping concentration (Na; p) adjacent to the trench ( ). To achieve this control, its dopant is provided after removing the spacers ( ) from the mask ( ) so as to form a doping window ( ), which may also be used for the source dopant, adjacent to the trench-gate ( ). A high energy dopant implant ( ) or other doping process provides this channel dopant adjacent to the trench ( ) and extending laterally below the mask ( ). A remarkably uniform doping profile can be achieved beneath the doping window ( ) and beneath the mask ( ). By using a high ion energy and high dose, the dopant ions ( ) at the doping window ( ) can be laterally scattered below the mask ( ) while those at the mask ( ) penetrate there-through to be implanted in the underlying portion of the body ( ).

Trench-gate semiconductor devices having a channel-accommodating region and their methods of manufacture

Compact trench-gate semiconductor devices, for example a cellular power MOSFET with sub-micron pitch (Yc), are manufactured with self-aligned techniques that use sidewall spacers ( ) in different ways. The trench-gate ( ) is accommodated in a narrow trench ( ) that is etched via a narrow window ( ) defined by the spacers ( ) at sidewalls of a wider window ( ) of a mask ( ) at the body surface ( ). The spacers ( ) permit a source region ( ) adjacent to the trench-gate ( ) and an insulating overlayer ( ) over the trench-gate ( ) to be self-aligned to this narrow trench ( ). The overlayer ( ), which defines a contact window ( ) for a source electrode ( ), is provided in a simple but reproducible manner by deposition and etch-back, after removing the spacers ( ). Its overlap (y , y &prime;) with the body surface ( ) is well-defined, so reducing a short-circuit risk between the source electrode ( ) and the trench-gate ( ). Furthermore, implantation of the source region ( ) is facilitated, and a channel-accommodating region ( ) can also be provided using a high energy implant ( ) after providing the insulating overlayer ( ).

Growing community of inventors

Stockport, United Kingdom

Georgios Petkos