Intel Corporation

Georgios Panagopoulos

James W Tschanz

Shih-Lien L Lu

Harald Gossner

Shigeki Tomishima

Wei Wu

Charles Augustine

Helia A Naeimi

Richard Geiger

Marko Radosavljevic

Han Wui Then

Sansaptak W Dasgupta

Thomas Wagner

Peter Baumgartner

Martin Ostermayr

Luis Giles

Klaus Herold

Joachim Singer

Johannes Rauh

Disclosed herein are IC devices, packages, and device assemblies that include III-N diodes with n-doped wells and capping layers. An example IC device includes a support structure and a III-N layer, provided over a portion of the support structure, the III-N layer including an n-doped well of a III-N semiconductor material having n-type dopants with a dopant concentration of at least 5×10dopants per cubic centimeter. The IC device further includes a first and a second electrodes and at least one capping layer. The first electrode interfaces a first portion of the n-doped well. The capping layer interfaces a second portion of the n-doped well and includes a semiconductor material with a dopant concentration below 10dopants per cubic centimeter. The second electrode is provided so that the capping layer is between the second portion of the n-doped well and the second electrode.

III-N diodes with n-doped wells and capping layers

A semiconductor structure is provided. The semiconductor structure includes a plurality of transistors arranged at a front side of a semiconductor substrate and a test structure located at the front side of the semiconductor substrate. Further, the semiconductor structure comprises a first electrically conductive connection extending from the test structure through the semiconductor substrate to a backside test pad arranged at a backside of the semiconductor substrate.

Semiconductor structure and method for forming a semiconductor structure

An apparatus is described that includes a semiconductor chip memory array having resistive storage cells. The apparatus also includes a comparator to compare a first word to be written into the array against a second word stored in the array at the location targeted by a write operation that will write the first word into the array. The apparatus also includes circuitry to iteratively write to one or more bit locations where a difference exists between the first word and the second word with increasing write current intensity with each successive iteration.

Magnetic storage cell memory with back hop-prevention

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Munich, Germany

Georgios Panagopoulos