Google Inc.

Oracle International Corporation

Georgios Konstadinidis

Michael David Hutton

Gaurav Agrawal

Safeen Huda

Lluis-Miquel Munguia

Alan P Smith

A method and system for controlling performance of a workload partitioned among a plurality of accelerator chips of a multi-chip system. One or more processors may receive performance speed data for each of the accelerator chips, obtain a model of the partitioned workload, determine a portion of the workload that is either overworked or underworked based on the model of the partitioned workload and the performance speed data for each of the plurality of accelerator chips, and adjust a performance speed of an accelerator chip that performs the portion of the partitioned workload that is either overworked or underworked.

Large-scale accelerator system energy performance optimization

A hardware-implemented hybrid analog-digital mixed-mode matrix multiply-add processing element (PE) for machine learning (ML) applications is disclosed. The hardware-implemented hybrid analog-digital mixed-mode matrix multiply-add PE for ML applications involves using Fin Field-Effect Transistors ('FinFETs'), which provide excellent sub-threshold operation, thereby reducing power requirements, and use variation minimization strategies to improve the overall accuracy. In this way, hybrid analog-digital mixed-mode matrix multiply-add calculations are efficient, low power, and accurate, with the processing element itself in a relatively small surface area.

Hardware-implemented hybrid analog-digital mixed-mode matrix multiply-add processing element for machine learning applications

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San Jose, CA, United States of America

Georgios Konstadinidis