Intel Corporation

Georgios C Dogiamis

Telesphor Kamgaing

Johanna M Swan

Adel A Elsherbini

Feras Eid

Sasha N Oster

Aleksandar Aleksov

Shawna M Liff

Henning Braunisch

Vijay K Nair

Neelam Prabhu Gaunkar

Brandon M Rawlings

Richard J Dischler

Thomas L Sounart

Diego Correas-Serrano

Valluri Ramana Rao

Hyung-Jin Lee

Erich Nolan Ewy

Veronica Aleman Strong

Emanuel Cohen

Gilbert W Dewey

Yoshihiro Tomita

Javier A Falcon

Qiang Yu

Kimin Jun

William J Lambert

Beomseok Choi

Stephen L Morein

Stefano Pellerano

Krishna Bharath

Kenneth D Shoemaker

David Johnston

Rachael Jade Parker

Baris Bicen

Ian A Young

Kristof Darmawikarta

Zhiguo Qian

Eric Jin Li

Gerald S Pasdast

Brandon C Marin

Fay Hua

Jeremy D Ecton

Rajashree Raji Baskaran

Suddhasattwa Nad

Jeff C Morriss

Alon Cohen

Christopher M Pelto

Cho-Ying Lu

Chintan S Thakkar

Ajay Balankutty

Ophir Shabtay

Sathya Narasimman Tiagaraj

Nicolas Butzen

Ahmed Abou-Alfotouh

Said Rami

Thomas W Brown

Cooper S Levy

Mohammad Mamunur Rahman

Jelena Culic-Viskota

Victor J Prokoff

David Harkness

Arun P Jose

Vivek Kumar Rajan

Jyothi Bhaskarr Velamala

Timothy Francis Schmidt

Kevin R Hoskins

Embodiments of the present disclosure provide a microelectronic assembly comprising: a first plurality of integrated circuit (IC) dies in a first layer; a second plurality of IC dies in a second layer; and a third layer between the first layer and the second layer, the third layer comprising conductive routing traces in a dielectric. A first interface is between the first layer and the third layer and includes first interconnects having a first pitch of less than 10 micrometers between adjacent ones of the first interconnects, a second interface is between the second layer and the third layer and includes second interconnects having a second pitch of less than 10 micrometers between adjacent ones of the second interconnects, and the routing traces in the third layer are to provide lateral electrical coupling between the first interconnects and the second interconnects.

Packaging architecture with intermediate routing layers

Embodiments described herein may be related to apparatuses, processes, and techniques related to contactless transmission within a package that combines radiating elements with vertical transitions in the package, in particular to a waveguide within a core of the package that is surrounded by a metal ring. A radiating element on one side of the substrate core and above the waveguide surrounded by the metal ring communicates with another radiating element on the other side of the substrate core and below the waveguide surrounded by the metal ring. Other embodiments may be described and/or claimed.

Contactless communication using a waveguide extending through a substrate core

Embodiments of a microelectronic assembly comprise a plurality of transceiver modules, each transceiver module including a first antenna; a printed circuit board (PCB); and a reflector module coupled to the PCB and separated from the plurality of transceiver modules by a space. The reflector module comprises: a substrate having a first side and an opposing second side, the first side being proximate to the plurality of transceiver modules, an antenna-array on the first side of the substrate, the antenna-array including a plurality of second antennas; a first integrated circuit (IC) die on the second side of the substrate; and a second IC die on the second side of the substrate. The first IC die comprises radio frequency (RF) switches configured to operate at electromagnetic frequencies between 20 kHz and 1 THz, and the second IC die comprises memory cell arrays and digital logic circuits.

High precision scalable packaging architecture based on radio frequency scanning

Methods and apparatus for inductor and transformer semiconductor devices using hybrid bonding technology are disclosed. An example semiconductor device includes a first standoff substrate; a second standoff substrate adjacent the first standoff substrate; and a conductive layer adjacent at least one of the first standoff substrate or the second standoff substrate.

Inductor and transformer semiconductor devices using hybrid bonding technology

A microelectronic assembly is provided comprising: a first IC die in a first layer comprising an array of radio frequency (RF) patch antennas on a side opposite to a second layer; a second IC die in the second layer between the first layer and a third layer; and a third IC die in the third layer. The first IC die comprises RF and analog circuitry, the first IC die is part of an array of IC dies having similar size and circuitry as the first IC die, the second layer and the third layer comprise a dielectric with through-dielectric vias (TDVs) therein surrounding the second IC die and the third IC die, respectively, and an interface between adjacent layers comprises interconnects having a pitch of 10 micrometers between adjacent interconnects.

Packaging architectures for sub-terahertz radio frequency devices

Embodiments disclosed herein include package substrates and methods of fabricating such substrates. In an embodiment, a package substrate comprises a core with a first surface and a second surface opposite from the first surface. The package substrate further comprises a via hole through the core. In an embodiment the via hole comprises a first portion, a second portion, and a perforated ledge between the first portion and the second portion. In an embodiment, the package substrate further comprises a via filling the via hole.

Physical vapor deposition seeding for high aspect ratio vias in glass core technology

Embodiments disclosed herein include coplanar waveguides and methods of forming coplanar waveguides. In an embodiment, a coplanar waveguide comprises a core, and a signal trace on the core. In an embodiment, the signal trace has a first edge and a second edge. In an embodiment, a first ground trace is over the core, and the first ground trace is adjacent to the first edge of the signal trace. In an embodiment, a first ground via plane is below the first ground trace. The coplanar waveguide may further comprise a second ground trace over the core, and the second ground trace is adjacent to the second edge of the signal trace. In an embodiment, a second ground via plane below the second ground trace.

Compact surface transmission line waveguides with vertical ground planes

A microelectronic assembly is provided, comprising: a first plurality of integrated circuit (IC) dies in a first level, each one of the first plurality of IC dies having respective first physical unclonable function (PUF) circuits; a second IC die having a second PUF circuit and a security circuit; a second plurality of IC dies in a second level, the second level not coplanar with the first level, the first level and the second level being coupled with interconnects having a pitch of less than 10 micrometers between adjacent ones of the interconnects; and conductive pathways between the first plurality of IC dies and the second IC die for communication between the first PUF circuits and the second PUF circuit, the conductive pathways comprising a portion of the interconnects.

Disaggregated entropy services for microelectronic assemblies

Embodiments disclosed herein include package substrates with filter architectures. In an embodiment, a package substrate comprises a core with a first surface and a second surface, and a filter embedded in the core. In an embodiment, the filter comprises a ground plane, where the ground plane is substantially orthogonal to the first surface of the core, and a resonator adjacent to the ground plane.

RF filters and multiplexers manufactured in the core of a package substrate using glass core technology

Embodiments of the present disclosure provide a microelectronic assembly comprising: an integrated circuit (IC) die in a first layer and a plurality of IC dies in a second layer, at least two adjacent IC dies in the plurality being electrically coupled along their proximate edges by the IC die. The first layer and the second layer are electrically and mechanically coupled by interconnects having a pitch of less than 10 micrometers between adjacent interconnects, and the IC die comprises capacitors and voltage regulator circuitry.

Power delivery through capacitor-dies in a multi-layered microelectronic assembly

Embodiments disclosed herein include package substrates and methods of forming such package substrates. In an embodiment the package substrate comprises a core and buildup layers on the core. In an embodiment, first level interconnect (FLI) pads are on a topmost buildup layer, and the FLI pads have a pitch. In an embodiment, a plurality of vertically oriented planes are embedded in the core, and the vertically oriented planes are spaced at the pitch.

Package substrate with glass core having vertical power planes for improved power delivery

Embodiments disclosed herein include electronic packages with magnetic features and methods of forming such packages. In an embodiment, a package substrate comprises a core and a conductive via through a thickness of the core. In an embodiment, a shell surrounds a perimeter of the conductive via and the shell is a magnetic material. In an embodiment, a surface of the conductive via is spaced away from the shell.

Magnetic planar spiral and high aspect ratio inductors for power delivery in the glass-core of a package substrate

Microelectronic assemblies, and related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a die-level interposer having a first surface and an opposing second surface; a first die coupled to the first surface of the die-level interposer by a first hybrid bonding region having a first pitch; a second die coupled to the second surface of the die-level interposer by a second hybrid bonding region having a second pitch different from the first pitch; and a third die coupled to the second surface of the die-level interposer by a third hybrid bonding region having a third pitch different from the first and second pitches.

Microelectronic assemblies having a hybrid bonded interposer for die-to-die fan-out scaling

Disclosed herein are waveguide interconnect bridges for integrated circuit (IC) structures, as well as related methods and devices. In some embodiments, a waveguide interconnect bridge may include a waveguide material and one or more wall cavities in the waveguide material. The waveguide interconnect bridge may communicatively couple two dies in an IC package.

Waveguide interconnect bridges

An integrated circuit (IC) package may be fabricated having an interposer, one or more microfluidic channels through the interposer, a first IC chip attached to a first side of the interposer, and a second IC chip attached to a second side of the interposer, where the first side of the interposer includes first bond pads coupled to first bond pads of the first IC chip, and the second side of the interposer includes second bond pads coupled to first bond pads of the second IC chip. In an embodiment of the present description, a liquid cooled three-dimensional IC (3DIC) package may be formed with the IC package, where at least two IC devices may be stacked with a liquid cooled interposer. In a further embodiment, the liquid cooled 3DIC package may be electrically attached to an electronic board. Other embodiments are disclosed and claimed.

Liquid cooled interposer for integrated circuit stack

Growing community of inventors

Chandler, AZ, United States of America

Georgios C Dogiamis