Intel Corporation

Georgios C Dogiamis

Telesphor Kamgaing

Johanna M Swan

Adel A Elsherbini

Feras Eid

Sasha N Oster

Aleksandar Aleksov

Shawna M Liff

Henning Braunisch

Vijay K Nair

Brandon M Rawlings

Richard J Dischler

Thomas L Sounart

Neelam Prabhu Gaunkar

Diego Correas-Serrano

Valluri Ramana Rao

Hyung-Jin Lee

Erich Nolan Ewy

Emanuel Cohen

Gilbert W Dewey

Yoshihiro Tomita

Javier A Falcon

William J Lambert

Beomseok Choi

Qiang Yu

Stefano Pellerano

Veronica Aleman Strong

Kenneth D Shoemaker

Baris Bicen

Stephen Morein

Ian A Young

Kristof Darmawikarta

Zhiguo Qian

Kimin Jun

Eric Jin Li

Fay Hua

Krishna Bharath

Brandon C Marin

Gerald S Pasdast

Rajashree Raji Baskaran

Jeremy D Ecton

Suddhasattwa Nad

David Johnston

Rachael Jade Parker

Jeff C Morriss

Cho-Ying Lu

Chintan S Thakkar

Ajay Balankutty

Ahmed Abou-Alfotouh

Said Rami

Nicolas Butzen

Thomas W Brown

Cooper S Levy

Mohammad Mamunur Rahman

Jelena Culic-Viskota

Victor J Prokoff

David Harkness

Arun P Jose

Vivek Kumar Rajan

Jyothi Bhaskarr Velamala

Timothy Francis Schmidt

Kevin R Hoskins

Embodiments of the present disclosure provide a microelectronic assembly comprising: an integrated circuit (IC) die in a first layer and a plurality of IC dies in a second layer, at least two adjacent IC dies in the plurality being electrically coupled along their proximate edges by the IC die. The first layer and the second layer are electrically and mechanically coupled by interconnects having a pitch of less than 10 micrometers between adjacent interconnects, and the IC die comprises capacitors and voltage regulator circuitry.

Power delivery through capacitor-dies in a multi-layered microelectronic assembly

Embodiments disclosed herein include package substrates and methods of forming such package substrates. In an embodiment the package substrate comprises a core and buildup layers on the core. In an embodiment, first level interconnect (FLI) pads are on a topmost buildup layer, and the FLI pads have a pitch. In an embodiment, a plurality of vertically oriented planes are embedded in the core, and the vertically oriented planes are spaced at the pitch.

Package substrate with glass core having vertical power planes for improved power delivery

Embodiments disclosed herein include electronic packages with magnetic features and methods of forming such packages. In an embodiment, a package substrate comprises a core and a conductive via through a thickness of the core. In an embodiment, a shell surrounds a perimeter of the conductive via and the shell is a magnetic material. In an embodiment, a surface of the conductive via is spaced away from the shell.

Magnetic planar spiral and high aspect ratio inductors for power delivery in the glass-core of a package substrate

Microelectronic assemblies, and related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a die-level interposer having a first surface and an opposing second surface; a first die coupled to the first surface of the die-level interposer by a first hybrid bonding region having a first pitch; a second die coupled to the second surface of the die-level interposer by a second hybrid bonding region having a second pitch different from the first pitch; and a third die coupled to the second surface of the die-level interposer by a third hybrid bonding region having a third pitch different from the first and second pitches.

Microelectronic assemblies having a hybrid bonded interposer for die-to-die fan-out scaling

Disclosed herein are waveguide interconnect bridges for integrated circuit (IC) structures, as well as related methods and devices. In some embodiments, a waveguide interconnect bridge may include a waveguide material and one or more wall cavities in the waveguide material. The waveguide interconnect bridge may communicatively couple two dies in an IC package.

Waveguide interconnect bridges

An integrated circuit (IC) package may be fabricated having an interposer, one or more microfluidic channels through the interposer, a first IC chip attached to a first side of the interposer, and a second IC chip attached to a second side of the interposer, where the first side of the interposer includes first bond pads coupled to first bond pads of the first IC chip, and the second side of the interposer includes second bond pads coupled to first bond pads of the second IC chip. In an embodiment of the present description, a liquid cooled three-dimensional IC (3DIC) package may be formed with the IC package, where at least two IC devices may be stacked with a liquid cooled interposer. In a further embodiment, the liquid cooled 3DIC package may be electrically attached to an electronic board. Other embodiments are disclosed and claimed.

Liquid cooled interposer for integrated circuit stack

Waveguide interconnects for semiconductor packages are disclosed. An example semiconductor package includes a first semiconductor die, a second semiconductor die, and a substrate positioned between the first and second dies. The substrate includes a waveguide interconnect to provide a communication channel to carry an electromagnetic signal. The waveguide interconnect is defined by a plurality of through substrate vias (TSVs). The TSVs in a pattern around the at least the portion of the substrate to define a boundary of the communication channel.

Waveguide interconnects for semiconductor packages and related methods

Disclosed herein are structures and assemblies that may be used for thermal management in integrated circuit (IC) packages.

Thermal management in integrated circuit packages

Disclosed herein are components for millimeter-wave communication, as well as related methods and systems.

Components for millimeter-wave communication

A microfluidic device having a channel within a first material to thermally couple with an IC die. The channel defines an initial fluid path between a fluid inlet port and a fluid outlet port. A second material is within a portion of the channel. The second material supplements the first material to modify the initial fluid path into a final fluid path between the fluid inlet port and the fluid outlet port. The second material may have a different composition and/or microstructure than the first material.

Modular microchannel thermal solutions for integrated circuit devices

A method of forming a waveguide comprises forming an elongate waveguide core including a dielectric material; and arranging a conductive sheet around an outside surface of the dielectric core to produce a conductive layer around the waveguide core.

Methods for conductively coating millimeter waveguides

An integrated circuit (IC) die package substrate comprises a first trace upon, or embedded within, a dielectric material. The first trace comprises a first metal and a first via coupled to the first trace. The first via comprises the first metal and a second trace upon, or embedded within, the dielectric material. A second via is coupled to the second trace, and at least one of the second trace or the second via comprises a second metal with a different microstructure or composition than the first metal.

High-throughput additively manufactured power delivery vias and traces

Embodiments of the invention include a microelectronic device that includes a first substrate having radio frequency (RF) components and a second substrate that is coupled to the first substrate. The second substrate includes a first conductive layer of an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher. A mold material is disposed on the first and second substrates. The mold material includes a first region that is positioned between the first conductive layer and a second conductive layer of the antenna unit with the mold material being a dielectric material to capacitively couple the first and second conductive layers of the antenna unit.

Microelectronic devices designed with mold patterning to create package-level components for high frequency communication systems

Embodiments may relate to a die such as an acoustic wave resonator (AWR) die. The die may include a first filter and a second filter in the die body. The die may further include an electromagnetic interference (EMI) structure that surrounds at least one of the filters. Other embodiments may be described or claimed.

Multi-filter die

Growing community of inventors

Chandler, AZ, United States of America

Georgios C Dogiamis