Cadence Design Systems, Inc.

Jasper Design Automation, Inc.

Georgia Penido Safe

Chung-Wah Norris Ip

Rajeev Kumar Ranjan

Kathryn Drews Kranen

Vincent Gregory Reynolds

Claudionor José Nunes Coelho

Adriana Cassia Rossi De Almeida Braz

Yann Alain Antonioli

Harry David Foster

Beth C Isaksen

Mirlaine Aparecida Crepalde

Guilherme Henrique De Sousa Santos

Yumi Monma

Fernanda Augusta Braga

Lucas Martins Chaves

Felipe Althoff

Pedro Bruno Neri Silva

Julio Alexandre Silva Rezende

Mariana Ferreira Marques

Devices, methods, computer readable media, and other embodiments are described for automated formal analysis and verification of a circuit design. One embodiment involves accessing a circuit design and a set of default verification targets for the circuit design. A plurality of partitions for the circuit design are then automatically generated, and a first partition is analyzed to generate a first set of verification targets for the first partition based on the set of default verification targets and a set of partition and schedule values for the first partition. A first formal verification analysis is performed on the first partition, the first set of verification targets, and the set of partition and schedule values, and a formal verification output is generated based on the first formal verification analysis. Various embodiments can additionally involve stagnation analysis and additional automation to customize the analysis for each partition.

Partition-based circuit analysis and verification

The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using a processor, an electronic design and providing at least a portion of the electronic design to a machine learning engine. Embodiments may further include automatically determining, based upon, at least in part, an output of the machine learning engine whether or not the at least a portion of the electronic design is amenable to formal verification.

System, method, and computer program product for determining suitability for formal verification

Disclosed are techniques for verifying connectivity of an electronic design. These techniques Identify connectivity information for a design description of an electronic design, generate a partition of a plurality of partitions for the connectivity information by partitioning the connectivity into the plurality of partitions based in part or in whole upon one or more factors, and performing a pre-proof verification flow on the partition by proving or disproving at least one connection candidate of a plurality of connection candidates for the partition to generate proof results for the partition. These techniques may further additionally generate a property for a connection candidate that fails to result in definitive proof results and prove or disprove the property with formal methods or techniques.

Methods, systems, and computer program product for connectivity verification of electronic designs

Disclosed are techniques for verifying X-behavior in electronic designs. These techniques identify at least a portion of an electronic design, wherein the at least the portion that includes an input node, an output node, and an internal node located between the input node and the output node. Internal X-propagation proof results may be generated for the internal node based in part or in whole upon an internal precondition and an internal harmless condition for the internal node. X-propagation verification for the output node may then be performed based in part upon one or more assumed properties at the internal node, wherein the one or more assumed properties are assumed at the internal node based in part or in whole upon the internal X-propagation proof results.

Methods, systems, and articles of manufacture for X-behavior verification of an electronic design

An executable circuit design is used to generate waveforms, from which behaviors of the circuit are captured. The behaviors and various combinations thereof can then be saved in a database, along with descriptions and other metadata about them, thereby generating a behavioral index of the circuit design code. Behavioral indexing of circuit designs allows a user to maintain an indexed behavior database, track changes in behaviors as the circuit design's executable description evolves, and figure out how the executable description can be reused in different projects. When applied to digital design development, it facilities the current design and verification effort, as well as design reuse down the line.

Isolating differences between revisions of a circuit design

Comprehending a circuit design

Generalizing and inferring behaviors of a circuit design

Growing community of inventors

Minas Gerais, Brazil

Georgia Penido Safe