Ferroelectric Memory Gmbh

Georgi Kuzmanov

Marko Noack

A ferroelectric memory circuit () includes: a memory cell (), wherein a memory state () of the memory cell () is switchable between a first memory state and a second memory state, the memory cell () further configured to output an electrical current () in response to receiving a readout voltage (); and a sense circuit () configured to output an output voltage () based on the result of integrating the electrical current () output by the memory cell (), wherein the output voltage () represents whether the memory state () is the first memory state or the second memory state.

Ferroelectric memory circuit and reading method thereof

Disclosed herein is a memory cell arrangement and method thereof for providing a reference read current for reading a plurality of memory cells. The memory cell arrangement includes a plurality of memory cells and one or more reference memory cells. The memory cell arrangement also includes a reference circuit that provides a reference read current for reading one or more of the plurality memory cells, wherein the reference circuit is connected to the one or more reference memory cells to generate the reference read current based on one or more reference currents from the one or more reference memory cells. The memory cell arrangement may also include a shifting circuit connected to the reference circuit, wherein the shifting circuit is configured to shift the reference read current.

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Dresden, Germany

Georgi Kuzmanov