Apple Inc.

Arm Finance Overseas Limited

Mips Technologies, Inc.

Georgi Beloev

Kevin D Kissell

Karagada Ramarao Kishore

Radhika Thekkath

James Hollabaugh

Zhiping Yang

Kirill Kalinichev

Girault W Jones

Greg Nayman

Songping Wu

Methods and apparatus for synchronization of integrated circuits (ICs) within a wireless network. In one embodiment, a serial time protocol (STP) is disclosed for use within a wireless device of a wireless network. The disclosed STP provides a common protocol for communicating precision time information from one time-transmitter IC to another time-receiver IC within a wireless device. In one exemplary implementation, a time-transmitter and a time-receiver are implemented within the firmware of a wireless device. Various schemes utilizing the disclosed STP for time synchronization are also described.

Methods and apparatus for synchronization among integrated circuits within a wireless network

System and method for performing a high-bandwidth memory copy. Memory transfer instructions allow for copying of data from a first memory location to a second memory location without the use of load and store word instructions thereby achieving a high-bandwidth copy. In one embodiment, the method includes the steps of (1) decoding a destination address from a first memory transfer instruction, (2) storing the destination address in a register in the bus interface unit, (3) decoding a source address from a second memory transfer instruction, and (4) copying the contents of a memory location specified by the source memory address to a memory location specified by the contents of the register. Other methods and a microprocessor system are also presented.

System and method for improving memory transfer

Methods and apparatus for equalization of a high speed serial bus. A well-tuned passive equalization circuit for use with high frequency differential signals suffer from e.g., impedance mismatches, impedance discontinuities (e.g., connectors, etc.). In one embodiment, a shunting circuit is inserted between the differential terminals of a Universal Serial Bus (USB) cable, connector, etc. The shunting circuit is configured to 'open' at low frequencies to enable Full Speed (FS) enumeration, while also providing sufficiently high impedance at high frequencies to enable High Speed (HS) operation. In one such implementation, the shunting circuit includes a tuned resistor, capacitor, inductor, and switch element arranged in series.

Methods and apparatus for equalization of a high speed serial bus

A RISC processor having a data moving engine and instructions that associate register addresses with memory addresses. In an embodiment, the instructions include a read-tie instruction, a single write-tie instruction, a dual write-tie instruction, and an untie instruction. The read-tie, single write-tie, and dual write-tie instructions are used to associate software accessible register addresses with memory addresses. These associations effect the operation of the data moving engine such that, for the duration of the associations, the data moving engine routes data to and from associated memory addresses and the execution unit of the processor in response to instructions that specify moving data to and from the associated register addresses. The invention reduces the number of instructions and hardware overhead associated with implementing program loops in a RISC processor.

Conditional branch execution in a processor having a data mover engine that associates register addresses with memory addresses

Growing community of inventors

Walnut Creek, CA, United States of America

Georgi Beloev