Intel Corporation

Microsoft Technology Licensing, LLC

Hewlett-packard Development Company, L.p.

George Zacharias Chrysos

Matthew Mattina

Ishwar Agarwal

Oscar Rosell Martinez

Krishnakanth Venkata Sistla

Edward Thomas Grochowski

Ankush Varma

Yen-Cheng Liu

Dheeraj R Subbareddy

Gerald S Pasdast

Vedaraman Geetha

Mahesh K Kumashikar

Jeffrey D Chamberlain

William R Halleck

Nevine Nassif

Tejpal Singh

Srikanth Nimmagadda

Carleton L Molnar

Siva Soumya Eachempati

John R Ayers

Francis X Mckeen

Raghunandan Makaram

Simon P Johnson

Amy L Santoni

Binata Bhattacharyya

Ramacharan Sundararaman

Chunhui Zhang

Ugonna C Echeruo

Jesus Corbal

Hong Wang

Shubhendu Sekhar Mukherjee

Per H Hammarlund

Yevgeniy Bak

Victor W Lee

Perry H Wang

Tryggve Fossum

Andrew Thomas Forsyth

Naveen K Mellempudi

John P Shen

Brian S Morris

Doron Orenstein

Michael D Upton

Federico Ardanaz

Steve Shih-wei Liao

Lisa K Wu

Todd Aldridge Dutton

Chung-Lun Chan

Jeffery A Brown

Siddhartha Chhabra

Simon C Steely, Jr

Joel S Emer

John H Crawford

William C Hasenplaugh

Dennis Ryan Bradford

John H Mylius

Aamer Jaleel

Yungho Choi

Chinmay Ashok

Paul B Racunas

Chuan-Hua Chang

Ching-kai Liang

Francis Tseng

Mohammed L Al-Aqrabawi

Stephen Felix

Peter Soderquist

Bhargavi Narayanasetty

Systems and methods related to direct swap caching with zero line optimizations are described. A method for managing a system having a near memory and a far memory comprises receiving a request from a requestor to read a block of data that is either stored in the near memory or the far memory. The method includes analyzing a metadata portion associated with the block of data, the metadata portion comprising: both (1) information concerning whether the near memory contains the block of data or whether the far memory contains the block of data and (2) information concerning whether a data portion associated with the block of data is all zeros. The method further includes instead of retrieving the data portion from the far memory, synthesizing the data portion corresponding to the block of data to generate a synthesized data portion and transmitting the synthesized data portion to the requestor.

Direct swap caching with zero line optimizations

Techniques of memory tiering include retrieving, from a first tier in a first memory, data from a data portion and metadata from a metadata portion of the first tier upon receiving a request to read data corresponding to a system memory section. The method can then include analyzing the data location information to determine whether the first tier currently contains data corresponding to the system memory section in the received request. In response to determining that the first tier currently contains data corresponding to the system memory section in the received request, transmitting the retrieved data from the data portion of the first memory to the processor in response to the received request. Otherwise, the method can include identifying a memory location in the first or second memory that contains data corresponding to the system memory section and retrieving the data from the identified memory location.

Memory tiering techniques in computing systems

Systems, methods, and apparatuses relating to a configurable accelerator having dataflow execution circuits are described. In one embodiment, a hardware accelerator includes a plurality of dataflow execution circuits that each comprise a register file, a plurality of execution circuits, and a graph station circuit comprising a plurality of dataflow operation entries that each include a respective ready field that indicates when an input operand for a dataflow operation is available in the register file, and the graph station circuit is to select for execution a first dataflow operation entry when its input operands are available, and clear ready fields of the input operands in the first dataflow operation entry when a result of the execution is stored in the register file; a cross dependence network coupled between the plurality of dataflow execution circuits to send data between the plurality of dataflow execution circuits according to a second dataflow operation entry; and a memory execution interface coupled between the plurality of dataflow execution circuits and a cache bank to send data between the plurality of dataflow execution circuits and the cache bank according to a third dataflow operation entry.

Apparatuses, methods, and systems for a configurable accelerator having dataflow execution circuits

Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.

Multiple dies hardware processors and methods

Techniques of memory tiering in computing devices are disclosed herein. One example technique includes retrieving, from a first tier in a first memory, data from a data portion and metadata from a metadata portion of the first tier upon receiving a request to read data corresponding to a system memory section. The method can then include analyzing the data location information to determine whether the first tier currently contains data corresponding to the system memory section in the received request. In response to determining that the first tier currently contains data corresponding to the system memory section in the received request, transmitting the retrieved data from the data portion of the first memory to the processor in response to the received request. Otherwise, the method can include identifying a memory location in the first or second memory that contains data corresponding to the system memory section and retrieving the data from the identified memory location.

Techniques of memory operations management are disclosed herein. One example technique includes retrieving, from a first memory, data from a data portion and metadata from a metadata portion of the first memory upon receiving a request to read data corresponding to a system memory section. The method can then include analyzing the data location information to determine whether the first memory currently contains data corresponding to the system memory section in the received request. In response to determining that the first memory currently contains data corresponding to the system memory section in the received request, transmitting the retrieved data from the data portion of the first memory to the processor in response to the received request. Otherwise, the method can include identifying a memory location in the second memory that contains data corresponding to the system memory section and retrieving the data from the identified memory location.

Memory operations management in computing systems

Methods and apparatuses relating to a vector instruction with a register operand with an elemental offset are described. In one embodiment, a hardware processor includes a decode unit to decode a vector instruction with a register operand with an elemental offset to access a first number of elements in a register specified by the register operand, wherein the first number is a total number of elements in the register minus the elemental offset, access a second number of elements in a next logical register, wherein the second number is the elemental offset, and combine the first number of elements and the second number of elements as a data vector, and an execution unit to execute the vector instruction on the data vector.

Hardware apparatuses and methods relating to elemental register accesses

A processor implementing techniques for supporting configurable security levels for memory address ranges is disclosed. In one embodiment, the processor includes a processing core a memory controller, operatively coupled to the processing core, to access data in an off-chip memory and a memory encryption engine (MEE) operatively coupled to the memory controller. The MEE is to responsive to detecting a memory access operation with respect to a memory location identified by a memory address within a memory address range associated with the off-chip memory, identify a security level indicator associated with the memory location based on a value stored on a security range register. The MEE is further to access at least a portion of a data item associated with the memory address range of the off-chip memory in view of the security level indicator.

Supporting configurable security levels for memory address ranges

Operations associated with a memory and operations associated with one or more functional units may be received. A dependency between the operations associated with the memory and the operations associated with one or more of the functional units may be determined. A first ordering may be created for the operations associated with the memory. Furthermore, a second ordering may be created for the operations associated with one or more of the functional units based on the determined dependency and the first operating of the operations associated with the memory.

Memory sequencing with coherent and non-coherent sub-systems

Systems and methods for memory protection for implementing trusted execution environment. An example processing system comprises: an on-package memory; a memory encryption engine (MEE) comprising a MEE cache, the MEE to: responsive to failing to locate, within the MEE cache, an encryption metadata associated with a data item loaded from an external memory, retrieve at least part of the encryption metadata from the OPM, and validate the data item using the encryption metadata.

Tree-less integrity and replay memory protection for trusted execution environment

Growing community of inventors

Portland, OR, United States of America

George Zacharias Chrysos