Chartered Semiconductor Manufacturing Ltd (corporation)

George Wong

Sik On Kong

Rajan Rajgopal

Johnny Cham

Cho Nam Hoon

Leong Chee Kong

Cheng Chor Shu

Pete Benyon

Neoh Soon Ee

Photolithographic methods for making liquid-crystal-on-silicon displays with alignment posts and optical interference layers

In accordance with the objectives of the invention a new methodology is provided that assures that integrated process results are verified and assured prior to the installation of processing tools as part of modifying or updating of a semiconductor manufacturing foundry. The complete semiconductor manufacturing complement of processing tools is sub-divided into short-loops or sub-modules, which are then combined into a full loop. This combination of sub-modules into modules that closer approach a full complement of processing tools can be accomplished in a gradual manner, whereby one or more sub-loops are first combined and evaluated, to this combination one or more additional sub-groups may be added whereby each of these latter sub-groups may also have been created by combining one or more (original) sub-loops. This process is continued to the point where a full complement of process equipment has been created, completing the full processing loops of the semiconductor manufacturing facility.

Methodology to obtain integrated process results prior to process tools being installed

A method for making a planar spin-on-glass (SOG) layer over integrated circuits at the corners of the chip (die) areas is achieved. This method allows more reliable integrated circuits to be made, and is particularly useful for liquid crystal displays (LCDs) by eliminating optical distortion at the corners of the LCD die areas. When a conducting layer is patterned to form portions of the integrated circuits over the chip areas, the layer is concurrently patterned to form a fill layer in the kerf areas. The spacing between the fill layer in the kerf areas and the edges of the patterned conducting layer in the die areas is selected to have a width sufficiently narrow to provide a uniform coating of SOG over the corners of the die areas without buildup of the SOG. After depositing a thin SiO,cap layer, a uniform SOG layer is deposited. The fill layer in the kerf areas also prevents dishing of the SOG layer when the SOG is chem-mech polished back. The process steps of this invention can be repeated to provide multilevels of electrical interconnections as required to complete the integrated circuits without causing non-uniformity of the SOG at the die corners.

Fill pattern in kerf areas to prevent localized non-uniformities of insulating layers at die corners on semiconductor substrates

A process for fabricating pixels and bonding pads wherein each has an optimal metal thickness in the fabrication of a LCD integrated circuit device is achieved. Semiconductor device structures are formed in and on a semiconductor substrate wherein the semiconductor device structures are covered by an insulating layer. A first metal layer is deposited overlying the insulating layer and patterned to form a metal line and a bonding pad. A dielectric layer is deposited overlying the metal line and the bonding pad. Vias are opened through the dielectric layer to the metal line but not to the bonding pad. A second metal layer is deposited overlying the dielectric layer and filling the via openings and etched back to form metal plugs. A third metal layer is deposited overlying the dielectric layer and metal plugs and patterned to form pixels contacting metal plugs. A passivation layer is deposited overlying the pixels. A via opening is etched through the passivation layer and the dielectric layer to the bonding pad. A wire bond is formed within the via opening to contact the bonding pad to complete the fabrication of the integrated circuit device.

Pad definition to achieve highly reflective plate without affecting

A method, and resultant structure, for manufacturing large highly reflective metal reflector plates on an integrated circuit chip, for applications in game chips or similar virtual image projection systems, is described. A metal interconnection layer is formed above a semiconductor substrate, an intermetal dielectric layer is formed on the metal interconnection layer, and an opening is made through the intermetal dielectric layer to expose a portion of the metal interconnection layer. A first metal layer is formed on the intermetal dielectric layer and connecting to the metal interconnection layer through the opening. A second metal layer is formed on the first metal layer. A third metal layer is formed on the second metal layer. A highly reflective metal layer is formed on the third metal layer. The the first, second, third and highly reflective metal layers are patterned to form the highly reflective metal reflector plate. A passivation layer is formed over the highly reflective metal reflector plate and exposed surface of the intermetal dielectric layer. The passivation layer is etched above the highly reflective metal reflector plate to leave a portion of the passivation layer over the entire top surface of the highly reflective metal reflector plate. The portion of the passivation layer is removed with a wet etch, to expose the highly reflective metal reflector plate.

Methods to fabricate large highly reflective metal reflector plates for

A structure formed by the method of forming a highly conductive electrical contact to a semiconductor region of an integrated circuits device is described. An opening to the semiconductor region is provided through an insulating layer. A thin first layer of aluminium having a first grain size is sputter deposited over and in the opening covering the surface of the semiconductor region. A second layer of aluminium having a second and substantially different grain size from the thin first layer of aluminium is sputter deposited thereover. The resulting aluminum structure is subjected in its normal process of manufacture to temperature cycling of greater than about 300.degree. C. whereby any formed silicon nodules are preferentially formed at the boundary of the thin first layer of aluminium and the second layer of aluminium. The second layer of aluminium may in one alternative completely fill the opening. In another alternative, a third layer has substantially the same grain size as the first aluminum. In this last alternative, the third layer will fill the opening to complete the electrical contact. The grain size is adjusted by the bias applied or not applied during the sputter deposition.

Integrated circuit aluminum contact structure to silicon device regions

A new method of metallization of an integrated circuit is described. Semiconductor device structures are fabricated in and on a semiconductor substrate. At least one contact opening to the semiconductor substrate and at least one lithography alignment cross mark opening structure are formed. A barrier layer is preferably sputtered within the contact openings and over the semiconductor device structures. A cold aluminum seed layer is sputtered over all surfaces of the contact openings. Next, a hot aluminum flow layer is provided to obtain the desired step coverage of the contact openings. A second cold aluminum layer is then sputtered onto the hot aluminum layer to define the edges of the wide lithography alignment marks while maintaining good contact opening coverage.

Metallization process for good metal step coverage while maintaining

The method of forming a highly conductive electrical contact to a semiconductor region of an integrated circuits device is described. An opening to the semiconductor region is provided through an insulating layer. A thin first layer of aluminium having a first grain size is sputter deposited over and in the opening covering the surface of the semiconductor region. A second layer of aluminium having a second and substantially different grain size from the thin first layer of aluminium is sputter deposited thereover. The resulting aluminum structure is subjected in its normal process of manufacture to temperature cycling of greater than about 300.degree. C. whereby any formed silicon nodules are preferentially formed at the boundary of the thin first layer of aluminium and the second layer of aluminium. The second layer of aluminium may in one alternative completely fill the opening. In another alternative, a third layer having substantially the same grain size as the first aluminum. In this last alternative, the third layer will fill the opening to complete the electrical contact. The grain size is adjusted by the bias applied or not applied during the sputter deposition.

Growing community of inventors

Singapore, Singapore

George Wong