Infineon Technologies Ag

Qimonda Ag

Infineon Technologies North America Corp.

Mitsubishi Electric and Electronics U.s.a., Inc.

George William Alexander

Torsten Partsch

Peter Gregorius

Hermann Ruckerbauer

Georg Braun

Johannes Stecker

Michael Bruennert

Steven Michael Baker

David SuitWai Ma

Jennifer Faye Huckaby

Thoai-Thai Le

Ben Heilmann

David Herbert

Andreas Gärtner

Andreas Gaertner

Jong-Hoon Oh

Jung Pill Kim

Ralf Klein

Stephen Michael Camacho

Guenter Gerstmeier

Eckhard Brass

Thoai Thai Le

James J Dietz

Stephen Charles Bowyer

Robert M Walker

Jinhwan Lee

Ronald Baker

Daivid SuitWai Ma

Distributed command and address bus architecture for memory modules and circuit boards is described. In one embodiment, a memory module includes a plurality of connector pins disposed on an edge of a circuit board, the plurality of connector pins comprising first pins coupled to a plurality of data bus lines, second pins coupled to a plurality of command and address bus lines, wherein the second pins are disposed in a first and a second region, wherein a portion of the first pins is disposed between the first and the second regions.

Distributed command and address bus architecture for a memory module having portions of bus lines separately disposed

A memory system includes a number of integrated circuit chips coupled to a bus. Each of the integrated circuit chips has an input/output node coupled to the bus, the input/output node having a programmable on-die termination resistor. The input/output node of one of the integrated circuit chips is accessed via the bus. The programmable on-die termination resistor of each of the integrated circuit chips is independently set to a termination resistance. The termination resistance is determined by a transaction type and which of the plurality memory devices is being accessed, which information can be transmitted over a separate transmission control bus.

Bus termination system and method

A method and multi-component electronic module device are provided that control the timing of output of data from a plurality of components on the multi-component module. One or more of the components are programmed to delay outputting data by a corresponding amount of time. In one embodiment, the one or more components are programmed such that all of the components output data at substantially the same time when they respond to a control signal. This is particularly useful for multi-component modules that are configured to respond to control signals in a so-called fly-by (or other) configuration that results in the control signal arriving at the components at different times causing the components to react to the control signal at different times.

Multi-component module fly-by output alignment arrangement and method

Memory devices and memory modules are disclosed. In one embodiment, a memory device includes a semiconductor substrate having a first edge and a second edge opposed to the first edge. A plurality of memory banks is disposed at a central portion of the semiconductor substrate, each memory bank including a plurality of memory cells. A plurality of input/output contacts is disposed between the first edge and the memory banks. Delay locked loop circuitry is disposed adjacent the first edge. A plurality of address and command contacts is disposed between the second edge and the memory banks.

High speed memory architecture

Horizontal dual in-line memory modules are disclosed. In one embodiment, the memory module includes a circuit board, a plurality of memory chips attached to a top surface of the circuit board, and a plurality of connector contacts disposed under a back surface of the circuit board and extending away from the memory chips, the connector contacts being electrically coupled to the memory chips, the back surface opposite the top surface of the circuit board.

Horizontal dual in-line memory modules

Methods and apparatuses for adjusting trim settings for internally generated voltages of an integrated circuit device are provided. In one embodiment the apparatus receives a target digital value for an internally generated voltage, and compares the target digital value to a current digital value for the internally generated voltage. If the comparison indicates that a difference between the target digital value and the current digital value is greater than an allowable threshold, a trim setting used to trim the internally generated voltage is adjusted based on the difference. The trim setting may be adjusted until the difference between the target digital value and the current digital value is less than or equal to the allowable threshold.

Implementation of a fusing scheme to allow internal voltage trimming

A method and circuit for controlling an output reference voltage generated by a reference voltage generator disposed on a memory device are provided. A signal for enabling a clocked standby mode of the memory device is received. If the signal indicates that the memory device is in the clocked standby mode, a first reference voltage is generated as the output reference voltage of the reference voltage generator using a first voltage. If the signal indicates that the memory device is not in the clocked standby mode, a second reference voltage is generated as the output reference voltage of the reference voltage generator using a second voltage.

Maintaining internal voltages of an integrated circuit in response to a clocked standby mode

Methods and apparatus for varying one or more internally generated voltages of a memory device based on the temperature of the memory device are provided. The device temperature may be measured directly, for example, via an on-chip temperature sensor, or may be supplied as bits in a mode register containing temperature information.

Internal voltage generator with temperature control

An off-chip driver (OCD) circuit and technique to reduce skew between rising and falling edges of output signals as process conditions vary are provided. Variations in process conditions may result in stronger or weaker relative current drive between NMOS and PMOS transistors. One or more process-dependent compensating current paths may be added to conventional pull-up and/or pull-down current paths to compensate for process variations by supplementing the current drive of transistors used to charge (PMOS) or discharge (NMOS) an output node of and end driver (e.g., inverter) stage of an OCD.

Method to improve current and slew rate ratio of off-chip drivers

A method and apparatus for controlling a voltage generator of a memory device are provided. A temperature of the memory device is measured. If the measured temperature is outside a threshold temperature range, the memory device is allowed to be placed in a clocked standby mode (CSM), whereby the voltage generator is selectively enabled with a clock signal. If the measured temperature is within a threshold temperature range, the memory device is prevented from being placed in the clocked standby mode (CSM).

Disabling clocked standby mode based on device temperature

A memory device includes a delay-locked loop circuit having delay elements and a synchronization circuit coupled to the delay-locked loop circuit. The synchronization circuit receives a synchronization enable signal and outputs a plurality of enable signals, including an enable signal coupled to an output circuit. Because the enable signal is synchronized with the read signal, it is possible to provide more time to read data into the buffer. A method of reading data from a memory device couples a synchronization enable signal and an external clock signal to a synchronization circuit. A read signal and an output enable are generated based upon a synchronization enable signal and a delayed clock signal of the external clock signal. Because the output signal is synchronized to the read signal, more time is allowed for the sense function.

Memory device and method of reading data from a memory device

A self-alignment system for complement clock signals includes a first delay circuit and a second delay circuit. A first clock signal may be propagated through the first delay circuit and a second clock signal may be propagated through the second delay circuit. A propagation delay of each of the first and second delay circuits may be selectively varied as a function of the first and second clock signals.

Self alignment system for complement clocks

A semiconductor wafer testing system tests one or more die clusters on a semiconductor wafer, using a test circuit to test multiple sections or areas of each die in parallel. The semiconductor wafer testing system has a buffer connected to the die cluster via the test circuit. The buffer writes test data onto a section of each die in the die cluster. The buffer reads test data from the section of each die in the die cluster.

Semiconductor wafer testing system

A system and method for monitoring internal voltage sources in an integrated circuit, such as a DRAM integrated circuit, includes an internal analog multiplexing circuit, an internal analog-to-digital converter, and an interface circuit. Through the analog multiplexing circuit, the analog-to-digital converter sequentially connects to each voltage source and converts the measured voltage level of the source to a binary word. The interface circuit presents the binary word, e.g., serially, to test equipment off the integrated circuit.

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Durham, NC, United States of America

George William Alexander