Cray Research, Inc.

George W Leedom

William T Moore, Jr

Alan J Schiffleger

Richard D Pribnow

Ram K Gupta

Galen C Flunker

Method and apparatus for a logical address translator which translates a logical address into a physical address in a computer. The computer includes a plurality of address ports. Each address port includes a logical address translator, which includes a plurality of segment-register sets. Each segment-register set holds values which specify address boundaries and translation mapping of a corresponding logical segment. A segment detector is coupled to the plurality of segment-register sets, wherein the segment detector operates to determine whether the logical address is within the specified address boundaries of the logical segment. An address mapper is coupled to the plurality of segment-register sets, wherein the address mapper operates to translate the logical address into a physical address. A translation controller is connected to the segment detector and the address translator, wherein the translation controller operates to output the physical address if the segment detector determines that the logical address is within the specified address boundaries of the logical segment. One embodiment of the segment-register set includes a base address, a limit address, and a physical mapping bias. One embodiment of the computer includes a plurality of address ports, wherein each address port includes a logical address translator.

Computer having multiple address ports, each having logical address

Method and apparatus for a scalar data cache in a scalar/vector supercomputer. The scalar data cache comprises a cache array and a cache controller. The cache array comprises a plurality of cache frames; each cache frame comprises a plurality of cache lines; and each cache line comprises a plurality of data words. The cache controller performs a broadside compare of the reference address against all addresses held in the cache, and translates the reference address into a cache-array address. For each cache line, there is a corresponding cache-line validity indication which is set 'valid' only when every data word in the cache line contains valid data. A cache-line validity comparator operates to provide a cache-line-hit indication if a data word requested is in a valid cache line. A cache-load controller is described for loading data from a common memory into every data word of a cache line and for marking the cache line 'valid'. For at least one of the plurality of scalar registers, a cache accessor is described for providing fetch access to the data words in the cache array, and for providing write-through-cache capability to the data words in the cache array.

Associative scalar data cache with write-through capabilities for a

Method and apparatus for vector processing on a computer system. As the last element of a group of elements (called a 'chunk') in a vector register is loaded from memory, the entire chunk is marked valid and thus made available for use by subsequent or pending operations. The vector processing apparatus comprises a plurality of vector registers, wherein each vector register holds a plurality of elements. For each of the vector registers, a validity indicator is provided wherein each validity indicator indicates a subset of the elements in the corresponding vector register which are valid. A chunk-validation controller is coupled to the validity indicators operable to adjust a value of the validity indicator in response to a plurality of elements becoming valid. An arithmetic logical functional unit (ALFU) is coupled to the vector registers to execute functions specified by program instructions. A vector register controller is connected to control the vector registers in response to program instructions in order to cause valid elements of a selected vector register to be successively transmitted to said ALFU, so that elements are streamed through said ALFU at a speed that is determined by the availability of valid elements from the vector registers. The ALFU optionally comprises a processor pipeline to hold operand data for operations not yet completed while receiving operands for successive operations. The ALFU also optionally comprises an address pipeline to hold element addresses corresponding to the operands for operations not yet completed while receiving element addresses corresponding to the operands for successive operations.

Vector register validity indication to handle out-of-order element

The present invention provides a vector processing computer system adapted for real-time I/O. The present invention combines a rotating priority interrupt scheme, dedicated real-time interrupt lines for each processor, and access to privileged communication/control modes of operation for processors operating in real-time to create a flexible hardware design adaptable for use in many different real-time applications.

Real time I/O operation in a vector processing computer system by

The present invention provides a memory interface system wherein there is provided a memory having multiple ports and divided into sections, with each section divided into subsections, with memory banks within each subsection, and the banks divided into at least two bank groups. The invention further provided a memory interface for controlling the referencing of said memory banks according to which bank group they are in.

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Jim Falls, WI, United States of America

George W Leedom