Intel Corporation

Tahoe Research, Ltd.

Sk Hynix Nand Product Solutions Corp.

George Vergis

Xiang Li

Kuljit Singh Bains

James A McCall

Bill Nale

Christopher E Cox

Phil Geng

Mohan J Kumar

Shigeki Tomishima

Kenneth Foust

Frank T Hady

Rajat Agarwal

Sarathy Jayakumar

Wei P Chen

Kirk S Yap

Murugasamy K Nachimuthu

Amit Kumar Srivastava

Raghunandan Makaram

Pete D Vogt

Zhichao Zhang

Sanka Ganesan

Ram S Viswanath

Jun Shi

Rajasekaran Swaminathan

Animesh Mishra

Jeffory L Smalley

Jacob Doweck

Chong J Zhao

Mani Prakash

Suneeta Sah

Douglas Heymann

John R Goles

Konika Ganguly

Rajesh Bhaskar

Emily P Chung

Dat Le

Navneet Dour

Myron Loewen

Joe Salmon

Jun Liao

John M Lynch

Matthew A Schnoor

Klaus J Ruff

Hany M Fahmy

Ge Chang

Jaejin Lee

Dimitrios Ziakas

Bassam N Coury

Kuang C Liu

David J Llapitan

Casey R Winkel

Suresh S Chittor

Gregorio R Murtagian

Sandeep K Jain

Janusz Jurski

Enrico David Carrieri

Yunhui Chu

Jonathan W Thibado

Jeffrey Krieger

Aiswarya M Pious

Charles C Phares

Phani Kumar Alaparthi

Guixiang Tan

Thomas T Holden

Qin Li

Raji James

Slobodan Mrdjan

Adam J Brooks

Hideo Oie

Girish C Venkatraman

An apparatus and method to monitor status of a serial data signal on a low speed serial bus is provided. A controller configures a watchdog timer in each target device, sends a heart-beat command to all of the target devices over the low speed serial bus prior to the expiration of the watchdog timer and issues a broadcast read command to any one of the target devices on the low speed serial bus. A response to the broadcast read command confirms that the low speed serial bus is functional. If a response is not received, the low speed serial bus is not functional and the controller initiates a broadcast reset command to initialize all target devices on the low speed serial bus.

Self-healing low speed serial interface

A memory module, a motherboard, and a latch assembly coupled to the memory module and the motherboard are described, the latch assembly including a connector coupled to the motherboard, a first lever coupled to the connector via a first pivot point, an load member extending through an opening in the first lever, a second lever coupled to the load member via a second pivot point, and a spring to bias the load member away from the opening in the first lever. The latch assembly may be used as a dual inline memory module (DIMM) retention assembly for compression mount technology (CMT) and land grid array (LGA) connector loading.

DIMM retention assembly for compression mount technology and land grid array connector loading

An embodiment of an electronic apparatus may comprise one or more substrates, and a controller coupled to the one or more substrates, the controller including circuitry to enumerate respective sideband addresses to ten or more memory devices, and provide bi-directional communication with an individual memory device of the ten or more memory devices with a particular sideband address enumerated to the individual memory device. Other embodiments are disclosed and claimed.

Memory device manageability bus

An apparatus is described. The apparatus includes a DIMM socket having a seating floor that is to meet both longer length contacts and shorter length contacts of a DIMM when the DIMM is fully seated in the socket.

DIMM socket with seating floor to meet both longer length edge contacts and shorter length edge contacts

An apparatus is described. The apparatus includes a power management integrated circuit (PMIC) to generate a supply voltage for a memory module. The PMIC is to perform a measurement during bring-up of the memory module of a worst case current draw of the memory module and/or corresponding droop in the supply voltage. The PMIC is to apply a step-up to the supply voltage in accordance with the measurement in response to detection by the PMIC of a surge in the memory module's current draw during operation of the memory module.

Method and apparatus for improved memory module supply current surge response

An apparatus is described. The apparatus includes a dual-in line memory module (DIMM) socket having a first latch and a second latch. One of the first latch and the second latch having a feature for a user to apply force to release a DIMM from the DIMM socket. The other of the first latch and the second latch not having a feature for the user to apply force so that one end of the DIMM releases before an opposite end of the DIMM during release of the DIMM from the DIMM socket.

Dual in-line memory module (DIMM) socket that prevents improper DIMM release

A connector includes connector pins that have a loop of conductor. The connector connects a first printed circuit board (PCB) to a second PCB with compression of the connector pins between the two boards. In response to compression of the connector, the connector pins make electrical contact with themselves through the loop, while also connecting pads of the first PCB to pads of the second PCB.

Closed loop compressed connector pin

Connectors with a hybrid pitch are described. In one example, a connector to couple a card or module to a motherboard includes connector housing and a plurality of pins. The plurality of pins include alternating signal and ground pins. Each of the plurality of pins includes a card or module-facing end to couple with the card or module and a lead to couple with a through hole in the motherboard. A first pitch between leads of a pin and a first adjacent pin is different than a second pitch between leads of the pin and a second adjacent pin.

Hybrid pitch through hole connector

Examples described herein relate to a pin arrangement that includes a first signal pin; a second signal pin; and multiple parallel ground pins positioned between the first and second signal pins. In some examples, the multiple parallel ground pins are coupled to a single pin connector coupled to a first device and a single pin connector coupled to a second device. In some examples, a first leg of the multiple parallel ground pins is positioned parallel to a portion of the first signal pin and wherein a second leg of the multiple parallel ground pins is positioned parallel to a portion of the second signal pin. In some examples, the multiple parallel ground pins provide a 1:N signal to ground ratio for signals transmitted through at least a portion of the first and second signal pins, where N is greater than 1.

Device-to-device connection with multiple parallel ground pins

An apparatus is described. The apparatus includes a register clock driver (RCD) semiconductor chip having first inputs to receive first command and address (CA) signals from a first sub-channel and first outputs to drive first and second instances of the CA information that are decoded from the first CA signals. The RCD semiconductor chip has second inputs to receive second command and address (CA) signals from a second sub-channel. The RCD semiconductor chip has a multiplexer having a first input channel to receive the first CA signals and a second input channel to receive the second CA signals. The RCD semiconductor chip has second outputs to drive third and fourth instances of the first CA information or first and second instances of the second CA information that are decoded from the second CA signals depending on which of the first and second input channels of the multiplexer is selected.

High performance memory module with reduced loading

An apparatus is described. The apparatus includes a printed circuit board (PCB) dual in-line memory module (DIMM) connector having ejectors. The ejectors have a small enough vertical profile to permit unbent liquid cooling conduits to run across the DIMM's semiconductor chips.

Reduced vertical profile ejector for liquid cooled modules

Examples described herein relate to a device that includes: a first power rail to provide a signal from a power source to a reference supply voltage pin of a memory controller; a second power rail to provide a signal from the power source to an output buffer pin of the memory controller and to an output buffer pin of a central processing unit (CPU). In some examples, the second power rail is separate from the first power rail, during a high power state, the power source is to supply a same voltage to each of the reference supply voltage pin, the output buffer pin of the memory controller, and the output buffer pin of the CPU, and during a connected standby state, the power source is to reduce voltage provided to the output buffer pin of the memory controller and the output buffer pin of the CPU using the second power rail and maintain a voltage provided to the reference supply voltage pin.

Power control of a memory device in connected standby state

Techniques to couple a high bandwidth memory device on a silicon substrate and a package substrate are disclosed. Examples include selectively activating input/out (I/O) or command and address (CA) contacts on a bottom side of a logic layer for the high bandwidth device based on a mode of operation. The I/O and CA contacts are for accessing one or more memory devices include in the high bandwidth memory device via one or more data channels.

Techniques to couple high bandwidth memory device on silicon substrate and package substrate

Connectors with a staggered pin orientation can reduce crosstalk amongst signal pins. In one example, a connector to couple a card or module to a motherboard includes connector housing and a plurality of pins. Each of the plurality of pins includes two ends including a card or module-facing end to couple with the card or module and a motherboard-facing end to couple with the motherboard. Each of the plurality of pins includes a middle section in the connector housing. One or both of the ends include one or more bends relative to the middle section. The plurality of pins includes alternating signal pins and ground pins, wherein the signal pins having an opposite orientation relative to the ground pins.

Connector with staggered pin orientation

An embodiment of a latch apparatus for a circuit board comprises a first latch body with a retention mechanism for the circuit board, a second latch body with a coupling mechanism for a connector, and a spring mechanism mechanically coupled between the first latch body and the second latch body. Other embodiments are disclosed and claimed.

Retention latch with spring mechanism

Growing community of inventors

Portland, OR, United States of America

George Vergis