Netapp, Inc.

Network Appliance, Inc.

Uatc, LLC

Uber Technologies, Inc.

Spinnaker Networks, Inc.

Utac, LLC

George Totolos, Jr

Joshua Oren Silberman

Carlos Vallespi-Gonzalez

Curtis Anderson

Tabriz Holtz

Joseph Lawrence Amato

Allen E Tracht

Scott Westbrook

Jeffrey S Kimmel

Rajesh Sundaram

Steve Miller

David Bruce Parlour

Daniel Leland Strother

Allen J Kilbourne, Ii

Michael W J Hordijk

Michael Hordijk

Nhiem T Nguyen

David Morgan Robles

Roger M Blood

Richard M Strong

Systems, methods, tangible non-transitory computer-readable media, and devices for autonomous vehicle operation are provided. For example, a computing system can receive object data that includes portions of sensor data. The computing system can determine, in a first stage of a multiple stage classification using hardware components, one or more first stage characteristics of the portions of sensor data based on a first machine-learned model. In a second stage of the multiple stage classification, the computing system can determine second stage characteristics of the portions of sensor data based on a second machine-learned model. The computing system can generate an object output based on the first stage characteristics and the second stage characteristics. The object output can include indications associated with detection of objects in the portions of sensor data.

Multiple stage image based object detection and recognition

In one example embodiment, a computer-implemented method includes obtaining sensor data from a sensor, the sensor data corresponding to an image frame, and the sensor data including a first portion that corresponds to a portion of the image frame. The method includes pipelining the first portion of the sensor data into a machine-learned model before the sensor data corresponding to the entire image frame is transferred from the sensor to a memory device, to perform one or more inference operations on the first portion of the sensor data. The method includes generating as an output of the machine-learned model, in response to pipelining the sensor data corresponding to each portion of the image frame into the machine-learned model, a detection or classification of the one or more objects indicated within the sensor data.

Systems and methods for pipelined processing of sensor data using hardware

Image processing systems can include one or more cameras configured to obtain image data, one or more memory devices configured to store a classification model that classifies image features within the image data as including or not including detected objects, and a field programmable gate array (FPGA) device coupled to the one or more cameras. The FPGA device is configured to implement one or more image processing pipelines for image transformation and object detection. The one or more image processing pipelines can generate a multi-scale image pyramid of multiple image samples having different scaling factors, identify and aggregate features within one or more of the multiple image samples having different scaling factors, access the classification model, provide the features as input to the classification model, and receive an output indicative of objects detected within the image data.

FPGA device for image classification

A method, non-transitory computer readable medium, and device that assists with sharing non-volatile memory solid state drives across a cluster group includes receiving a request for a block of storage in a non-volatile memory solid state drive in one of the plurality of non-volatile memory disk shelves. Information associated with each of a plurality of solid state drives in the plurality of non-volatile memory disk shelves associated with the received request is obtained. A namespace for each of the plurality of solid state drives in the plurality of non-volatile memory disk shelves using the obtained information is created. The requested block of storage in the non-volatile memory solid state drive associated with one of the created namespace is assigned to the requesting client computing device.

Methods for sharing NVM SSD across a cluster group and devices thereof

One or more techniques and/or systems are provided for multicast transport configuration, for multicast transport, and/or for fault policy implementation. In an example, a multicast component may receive a data copy request from an application to copy data to multiple destinations. A scheduler component may create a transport schedule specifying an order with which to facilitate data copy operations across transports, such as heterogeneous transports, to the destinations. A dispatcher component may apply application specified transport modifiers to the data copy operations (e.g., a modification to a quality of service for a transport). The dispatcher component may facilitate the data copy operations and provide operation result information to a policy agent. The policy agent may provide notifications of data copy operation statuses from the operation result information and/or may implement a fault policy (e.g., a retry on a different transport) for a data copy operation that experienced a fault.

Multicast transport

Multicast transport configuration

Fault policy implementation

In an aspect of the subject matter, a 'full' amount of the flash cache (e.g., storage cells) is initially utilized to store data i.e., substantially all of the storage space of the flash cache may be designated to store user data, with the remaining storage space designated to store ECC information (e.g., parity bits) associated with a predefined ECC algorithm utilized to encode the user data. When a bit errors associated with the user data reaches a predefined threshold value, the storage space of the flash cache may transition to store less user data so as to accommodate the space needed to store ECC information associated with a stronger ECC algorithm. The storage space of the flash cache designated to store user data is reduced, while the storage space designated to store ECC information is increased to accommodate the stronger ECC algorithm.

Adaptively strengthening ECC for solid state cache

Improved power management techniques for computer-readable storage devices are described. In one embodiment, for example, an apparatus may comprise a plurality of logical storage devices and a controller to manage operations of the plurality of logical storage devices, the controller comprising a configuration component to configure a global power consumption threshold defining an overall power consumption budget for the plurality of logical storage devices, a tracking component to maintain a global power consumption tally comprising an estimated total power consumption level for the plurality of logical storage devices, and an arbitration component to resolve an operation request based on the global power consumption threshold and the global power consumption tally. Other embodiments are described and claimed.

Power management techniques for computer-readable storage devices

Examples are disclosed for assessing pass/fail status of non-volatile memory. In some examples, information may be received to indicate a block having memory pages associated with non-volatile memory cells. The information may indicate at least some of the memory pages have bit errors in excess of an error correction code (ECC) ability to correct. For these examples, the block may be selected for read testing. Read testing may include programming the memory pages with a known pattern and waiting a period of time. Following the period of time each memory page may be read and if a resulting pattern read matches the known pattern programmed to each memory page, the memory page passes. The block may be taken offline if the number of passing memory pages is below a pass threshold number. Other examples are described and claimed.

Techniques for assessing pass/fail status of non-volatile memory

Described herein are method and apparatus for scheduling access requests for a multi-bank low-latency random read memory (LLRRM) device within a storage system. The LLRRM device comprising a plurality of memory banks, each bank being simultaneously and independently accessible. A queuing layer residing in storage system may allocate a plurality of request-queuing data structures ('queues'), each queue being assigned to a memory bank. The queuing layer may receive access requests for memory banks in the LLRRM device and store each received access request in the queue assigned to the requested memory bank. The queuing layer may then send, to the LLRRM device for processing, an access request from each request-queuing data structure in successive order. As such, requests sent to the LLRRM device will comprise requests that will be applied to each memory bank in successive order as well, thereby reducing access latencies of the LLRRM device.

Scheduling access requests for a multi-bank low-latency random read memory device

Growing community of inventors

Cranberry Township, PA, United States of America

George Totolos, Jr