Intel Corporation

George Thangadurai

Suresh K Marisetty

Mani Ayyar

Amy L O'Donnell

Anand Rajan

Stephen H Gunther

Andrew J Fish

Sham M Datta

Yan Li

Chih-Hung Chung

Stanley J Domen

Vijay Kumar Goru

Richard W Goe

Dileep R Idate

Erik T Lode

A system comprises a non volatile memory and a plurality of processors. The non volatile memory stores an error handling routine. Each processor of the plurality of processors accesses the error handling routine on detecting an error and, on certain errors, signals the remaining processors to enter a rendezvous state. In the rendezvous state, a single processor takes over and performs error handling.

Error correction apparatus, systems, and methods

A method and an apparatus for restoring logic states using programming code are disclosed. In one embodiment, the process of a data processing system identifies a first logic value stored in a first register and branches to a first location within the programming code based upon the first logic value. The execution of the programming code occurs in a processor firmware layer. The first register can be used as a scratch register for the subsequent instruction.

Method and apparatus to save processor architectural state for later process resumption

Algorithm for non-volatile memory updates

A method and an apparatus for validating a processor firmware (&ldquo;PF&rdquo;) are disclosed. In one embodiment, at least one version of Processor Firmware (&ldquo;PF&rdquo;) is identified. After identification, the PF is compared with a version of PF that is required by a processor, to determine whether the PF is compatible with the processor. If the version of PF is incompatible with the version of PF required by the processor, the current execution is suspended and a new version of PF is obtained. When the new version of PF is received, the system is initialized.

CPU stepping and processor firmware matching mechanism

Rendezvous of processors with OS coordination

An electronic system and corresponding method for verifying the integrity of code that is stored off-chip. The electronic system comprises a memory element to store Processor Abstraction Layer (PAL) code and a processor coupled to the memory element. The processor verifies the integrity of the PAL code prior to execution of the PAL code.

System and method for verification of off-chip processor code

An electronic system and corresponding method for authenticating firmware stored in a memory element external to a processor. In one embodiment, an electronic system comprises a processor and a memory element. The memory element is used to contain firmware and a digital signature of the firmware signed by a signatory. Coupled to the memory element, the processor authenticates the firmware during a predetermined condition, which occurs prior to execution of the firmware, through use of a pre-stored public key of the signatory and a pre-stored digital signature function.

System and method for authentication of off-chip processor firmware code

A system and method is provided for processing interrupt requests. The method is accomplished by detecting when an interrupt request is being stored in a storage location, examining the storage location storing the interrupt request, prioritizing the interrupt request when more than one interrupt request is stored in the storage location to determine an interrupt request processing order, clearing the interrupt request in the storage location that is to be processed, and processing the interrupt request. The system comprises a first storage location for storing an interrupt request, a second storage location for storing an interrupt handler program with encoded statements for examining the first storage location, prioritizing the interrupt request that is to be processed if more than one interrupt request is stored in said first storage location, clearing the interrupt request that is to be processed, and processing the interrupt request. The system further comprises a processor for executing the interrupt handler program.

Method and apparatus for processing more than one interrupts without

An apparatus and method for dynamically adjusting the power/performance characteristics of a memory subsystem. Since the memory subsystem access requirements are heavily dependent on the application being executed, static methods of enabling or disabling the individual memory system components (as are used in prior art) are less than optimal from a power consumption perspective. By dynamically tracking the behavior of the memory subsystem, the invention predicts the probability that the next event will have certain characteristics, such as whether it will result in a memory cycle that requires the attention of a cache memory, whether that memory cycle will result in a cache memory hit, and whether a DRAM page hit in main memory will occur if the requested data is not in one of the levels of cache memory. Based on these probabilities, the invention dynamically enables or disables components of the subsystem. By intelligently adjusting the state of these components, significant power savings are achieved without degradation in performance.

Method and apparatus for dynamically adjusting power/performance

A microprocessor includes the capability to service at least one debug exception and an I/O trap generated during execution of a single instruction. After executing each instruction, the microprocessor determines whether a debug exception and an I/O trap occurred. If at least one debug exception and an I/O trap exist, then the microprocessor determines an active status for the debug exception. The microprocessor stores the contents of internal registers, constituting a state of the microprocessor, to memory, and latches a breakpoint status for the debug exception in a public debug status register. The breakpoint status is preserved by copying the breakpoint status to a private debug status register. The microprocessor services the I/O trap by executing a SMM handler, an upon returning from the SMM handler, the state of the microprocessor is restored. If the I/O trap serviced requires instruction restart, then the state of the microprocessor is adjusted to re-execute the instruction. The microprocessor copies the breakpoint status, stored in the private debug status register, to the public debug status register when the I/O trap does not require instruction restart. The debug exception is subsequently serviced by executing an INT1 handler.

Growing community of inventors

Santa Clara, CA, United States of America

George Thangadurai