Sandisk Corporation

Sandisk 3d LLC

Sandisk Technologies Inc.

Sunrise Memory Corporation

Sundisk Corporation

George Samachisa

Eli Harari

Jack H Yuan

Daniel C Guterman

Johann Alsmeier

Roy E Scheuerlein

Henry Chien

James K Kai

Tianhong Yan

Wu-Yi Henry Chien

Chi-Ming Wang

Brian Murphy

George Matamis

Yupin K Fong

Luca Giovanni Fasoli

Vinod Robert Purayath

Khandker N Quader

Andrei Mihnea

Yuan Zhang

Christopher John Petti

Peter Rabkin

Raul Adrian Cernea

John S Mangan

Donovan Lee

Deepak Chandra Sekar

Yan Li

Masaaki Higashitani

Jian Feng Chen

Yanli Zhang

Henry Chin

Sanjay Mehrotra

Yung-Tin Chen

Stephen Jeffrey Gross

Sayeef Salahuddin

Li Xiao

Winston Lee

Vinod Purayath

Raghuveer S Makala

Er-Xuan Ping

Scott Brad Herner

Raul-Adrian Cernea

Tanmay Kumar

Yao-Sheng Lee

Franz Kreupl

Wipul Jayasekara

Bing K Yen

Tz-Yi Liu

Abhijit Bandyopadhyay

Huiwen Xu

Perumal Ratnam

Xiying Chen

Jingyan Zhang

Chu-Chen Fu

Dat Nguyen

Tim Chen

Wipul Pemsiri Jayasekara

Roy Edwin Scheuerlein

Daniel C Gutermann

A thin-film storage transistor in a NOR memory string has a gate dielectric layer that includes a silicon oxide nitride (SiON) tunnel dielectric layer. In one embodiment, the SiON tunnel dielectric layer has a thickness between 0.5 to 5.0 nm thick and an index of refraction between 1.5 and 1.9. The SiON tunnel dielectric layer may be deposited at between 720° C. and 900° C. and between 100 and 800 mTorr vapor pressure, using an LPCVD technique under DCS, NO, and NHgas flows. The SiON tunnel dielectric layer may have a nitrogen content of 1-30 atomic percent (at %).

Silicon oxide nitride tunnel dielectric for a storage transistor in a 3-dimensional NOR memory string array

A storage transistor has a tunnel dielectric layer and a charge-trapping layer between a channel region and a gate electrode, wherein the charge-tapping layer has a conduction band offset that is less than the lowering of the tunneling barrier in the tunnel dielectric layer when a programming voltage is applied, such that electrons direct tunnel into the charge-trapping layer. The conduction band of the charge-trapping layer has a value between −1.0 eV and 2.3 eV. The storage transistor may further include a barrier layer between the tunnel dielectric layer and the charge-trapping layer, the barrier layer having a conduction band offset less than the conduction band offset of the charge-trapping layer.

Cool electron erasing in thin-film storage transistors

Thin-film Ferroelectric field-effect transistor (FeFET) may be organized as 3-dimensional NOR memory string arrays. Each 3-dimensional NOR memory string array includes a row of active stack each including a predetermined number of active strips each provided one on top of another and each being spaced apart from another by an isolation layer. Each active strip may include a shared source layer and a shared drain layer shared by the FeFETs provided along the active strip. Data storage in the active strip is provided by ferroelectric elements that can individually electrically set into one of two polarization states. FeFETs on separate active strips may be configured for read, programming or erase operations in parallel.

Three-dimensional memory string array of thin-film ferroelectric transistors

3-dimensional memory string array of thin-film ferroelectric transistors

A storage transistor has a tunnel dielectric layer and a charge-trapping layer between a channel region and a gate electrode, wherein the charge-tapping layer has a conduction band offset that is less than the lowering of the tunneling barrier in the tunnel dielectric layer when a programming voltage is applied, such that electrons direct tunnel into the charge-trapping layer. The conduction band of the charge-trapping layer is has a value between &#x2212;1.0 eV and 2.3 eV. The storage transistor may further include a barrier layer between the tunnel dielectric layer and the charge-trapping layer, the barrier layer having a conduction band offset less than the conduction band offset of the charge-trapping layer.

A thin-film storage transistor includes (a) first and second polysilicon layers of a first conductivity serving, respectively, as a source terminal and a drain terminal of the thin-film storage transistor; (b) a third polysilicon layer of a second conductivity adjacent the first and second polysilicon layers, serving as a channel region of the thin-film storage transistor; (c) a conductor serving as a gate terminal of the thin-film storage transistor; and (d) a charge-trapping region between the conductor and third polysilicon layer, wherein a fourth body layer polysilicon of the second conductivity is included to provide an alternative source of free charge careers to accelerate device operation.

Device structure for a 3-dimensional NOR memory array and methods for improved erase operations applied thereto

A non-volatile 'reverse memory cell' suitable for use as a building block for a 3-dimensional memory array includes a charge-trapping layer which is programmed or charged through gate-injection, rather than channel-injection. Such a reverse cell may be implemented as either an n-channel memory cell or a p-channel memory cell, without incurring design or process penalties, or any complexity in programming or erase operations. Furthermore, all reading, programming, erase, program-inhibiting operations may be carried out in the reverse memory cell using only positive or only negative voltages, thereby simplifying both the design and the power management operations.

Reverse memory cell

A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a single-sided word line architecture

Methods for performing memory operations on a memory array that includes inverted NAND strings are described. The memory operations may include erase operations, read operations, programming operations, program verify operations, and erase verify operations. An inverted NAND string may include a string of inverted floating gate transistors or a string of inverted charge trap transistors. In one embodiment, an inverted floating gate transistor may include a tunneling layer between a floating gate of the inverted floating gate transistor and a control gate of the inverted floating gate transistor. The arrangement of the tunneling layer between the floating gate and the control gate allows electrons to be added to or removed from the floating gate via F-N tunneling between the floating gate and the control gate. The inverted NAND string may be formed above a substrate and oriented such that the inverted NAND string is orthogonal to the substrate.

Operation modes for an inverted NAND architecture

Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines

A memory device and a method of making a memory device that includes a semiconductor channel, a tunnel dielectric layer located over the semiconductor channel, a floating gate located over the tunnel dielectric layer, the floating gate comprising a continuous layer of an electrically conductive material and at least one protrusion of an electrically conductive material facing the tunnel dielectric layer and electrically shorted to the continuous layer, a blocking dielectric region located over the floating gate, and a control gate located over the blocking dielectric layer.

Nanodot enhanced hybrid floating gate for non-volatile memory devices

A three-dimensional array of memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array includes a two-dimensional array of pillar lines from the substrate through the multiple layers of planes. A first set of pillar lines acts as local bit lines for accessing the memory elements together with an array of word lines on each plane. A second set of pillar lines is connected to the word lines. An array of metal lines on the substrate is switchable connected to the pillar lines to provide access to the first and second sets of pillar lines, thereby to provide access respectively to the bit lines and word lines of the three-dimensional array.

Method for non-volatile memory having 3D array of read/write elements with efficient decoding of vertical bit lines and word lines

A non-volatile storage device comprises: a substrate; a monolithic three dimensional array of memory cells; word lines connected to the memory cells; global bit lines; vertical bit lines connected to the memory cells; and a plurality of double gated vertically oriented select devices. The double gated vertically oriented select devices are connected to the vertical bit lines and the global bit lines so that when the double gated vertically oriented select devices are activated the vertical bit lines are in communication with the global bit lines. Each double gated vertically oriented select device has two gates that are offset from each other with respect to distance to the substrate. Both gates for the double gated vertically oriented select device need be in an 'on' condition for the double gated vertically oriented select devices to be activated.

Shared-gate vertical-TFT for vertical bit line array

A three-dimensional memory is formed as an array of memory elements across multiple layers positioned at different distances above a semiconductor substrate. Cylindrical stacks of memory elements are formed where a cylindrical opening has read/write material deposited along its wall, and a cylindrical vertical bit line formed along its central axis. Memory elements formed on either side of such a cylinder may include sheet electrodes that extend into the read/write material.

Memories with cylindrical read/write stacks

Growing community of inventors

San Jose, CA, United States of America

George Samachisa