Silicon Graphics, Incorporated

Mips Computer Systems, Inc.

George S Taylor

Allen W Roberts

Timothy P Layman

P Michael Farmwald

Huy X Ngo

David M Parry

Michael P Farmwald

David B Roberts

A method of invalidating a line in a designated cache in each level of a multiple level, multiple cache memory system. Each line of the cache memory system includes a tag field, a data field, and a bit indicative of the validity of the line. The method provides a software invalidate instruction which bypasses any address translation mechanism. Included in the software invalidate instruction is a first field to identify within which multiple cache the line is to be avoided. A target address is generated to index each level of the cache memory system. The state of the bit is changed in accordance with the address and the invalidate instruction.

Software invalidation in a multiple level, multiple cache system

Methods and apparatus for optimizing the operation of an instruction pipeline in a computer are disclosed. The methods and apparatus function at both the effective beginning and end of the pipeline. At the pipeline's beginning, a Pipeline Controller monitors the availability of data for various floating point operations. Data is read at either a fast or slow rate, depending on its availability, and instructions are allowed to proceed through the pipeline based on this data availability. At the effective end of the pipeline, the Controller monitors all instructions in the pipeline, notes all potential resource conflicts, and resolves these potential conflicts by either the insertion of an appropriate number of HOLD states or the conclusion that no actual resource competition exists.

Rescheduling conflicting issued instructions by delaying one conflicting

A two-level cache memory system for use in a computer system including two primary cache memories, one for storing instruction and one for storing data. The system also includes a secondary cache memory for storing both instructions and data. The primary and secondary caches each employ their own separate tag directory. The primary caches use a virtual addressing scheme employing both virtual tags and virtual addresses. The secondary cache employs a hybrid addressing scheme which uses virtual tags and partial physical addresses. The primary and secondary caches operate in parallel unless the larger and slower secondary cache is busy performing a previous operation. Only if a 'miss' is encountered in both the primary and secondary caches does the system processor access the main memory.

Cache memory system employing virtual address primary instruction and

A two-level cache memory system for use in a computer system including two primary cache memories, one for storing instructions and one for storing data. The system also includes a secondary cache memory for storing both instructions and data. The primary and secondary caches each employ their own separate tag directory. The primary caches use a virtual addressing scheme employing both virtual tags and virtual addresses. The secondary cache employs a hybrid addressing scheme which uses virtual tags and partial physical addresses. The primary and secondary caches operate in parallel unless the larger and slower secondary cache is busy performing a previous operation. Only if a 'miss' is encountered in both the primary and secondary caches does the system processor access the main memory.

Two-level cache memory system

A translation of a portion of a virtual page number to a portion of a physical page number in a 'TLB slice.' The slice translation is used to index into a physical cache memory which has virtual tags in addition to physical tags and whose addresses are physical. By comparing the virtual tag to the input virtual address page number, it can be determined whether there was a hit or a miss in the combination of the TLB slice and the cache memory. By translating only a few bits of the virtual address to a few bits of a physical address, the speed of the device is greatly enhanced. This increased speed is achieved by making the TLB slice direct-mapped and by taking advantage of its small size to build it with special hardware (either high-speed RAM (random access memory) or with latches and multiplexers). There is no separate comparison at the TLB slice output for determining a TLB slice hit. The subsequent cache tag comparison is used to indicate both whether the translation was correct and whether there was a cache hit. To achieve this dual purpose comparison, however, a virtual tag must be combined with a physical cache to determine whether there is a hit, since the entire virtual address has not been translated and therefore there is no translated physical address to compare with a physical tag.

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Menlo Park, CA, United States of America

George S Taylor