Hughes Aircraft Company

George S Des Brisay, Jr

Iradj Shahriary

Victor S Reinhardt

Kim V Gould

Susan K Avery

A phase lock loop frequency synthesizer for providing a synthesized frequency signal employing a modified adaptive loop construction having parallel feedback paths about a loop amplifier. A normal feedback path having a narrow bandwidth characteristic includes a feedback capacitor having one end connected to electrical ground via a controlled switch and a second feedback path having a wide bandwidth characteristic with a capacitor also connected across the amplifier. Upon the variation of an incoming reference signal, the controlled switch connects the normal feedback capacitor to ground permitting the wide bandwidth feedback path to rapidly settle the loop while charging the feedback capacitor of the normal feedback path. Upon opening the controlled switch, the narrow bandwidth feedback path completes the charging of the feedback capacitor of the normal feedback loop settling the loop to the steady state condition while enhancing the settling time.

Fast settling phase lock loop

An improved cascadable adder (11) which, through the use of merged logic, provides high speed operation in the presence of input loading and internal fan-out limitations. The invention may be implemented in gallium arsenide technology and includes a first circuit (13) for exclusive ORing first bits (A.sub.1, B.sub.1) of first and second digital words (A, B) respectively; and a second circuit (37) operatively connected to the first circuit (13) for generating, with only two gate delays, a carry (C.sub.1) associated with the summing of the first bits.

High speed adder

A digital phase frequency discriminator is disclosed that eliminates crossover distortion problem inherent in previous discriminator without a corresponding increase in complexity in the circuit. The discriminator includes four cross-coupled RS latches and a reset gate. The reset gate is coupled to the latches such that additional gate delays are provided to ensure that the output signals of the discriminator reach these full logic amplitude and thereby allow for accurate phase frequency discrimination to occur.

Digital phase-frequency discriminator comprising simplified reset means

An integrated circuit latch is provided for providing first and second output signals, each first output signal being a logical complement of a corresponding second output signal; the latch includes means for receiving a first clock signal; means for receiving a corresponding second clock signal, the second clock signal being a logical complement of the first clock signal; means for receiving N first data signals, where N is an integer and N&lt;1; means for receiving N second data signals, where each second data signal corresponds to a first data signal and is the logical complement of a corresponding first data signal; NOR-OR logic function means for providing the first output signal characterized by the OR function of first and second logic inputs, the first logic input characterized by the NOR function of the second output and the second clock signal, the second logic input characterized by the NOR function of the first data signals and the first clock signal; and NAND-AND logic function means for providing the second output signal characterized by the AND function of third and fourth logic inputs, the third logic input characterized by the NAND function of the first output signal and the first clock signal, said fourth logic input characterized by the NAND function of the second data signals and the second clock signal.

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Hemet, CA, United States of America

George S Des Brisay, Jr