Compaq Computer Corporation, Inc.

George S Checkowski

Daniel Wissell

A load-insensitive circuit enables a global reference clock signal source of a synchronous multiprocessor system having a plurality of nodes to be &ldquo;insensitive&rdquo; with respect to the insertion or removal (&ldquo;hot-swap&rdquo;) of a load (such as a node) when the system is operational. The load insensitive clock source is provided through the use of a customized two-way passive radio frequency power splitter having an input port and two phase-matched output ports. A high degree of isolation is provided between clock signals delivered over the output ports when the input port of the splitter is properly terminated and embedded in a controlled impedance environment. Isolation is further enhanced by terminating each output port with a constant impedance comprising a precisely-matched, 50-ohm impedance load pad.

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Acton, MA, United States of America

George S Checkowski