Harris Corporation

Intersil Americas Inc.

Intersil Corporation

George S Bajor

Anthony L Rivoli

Donald Frank Hemmenway

George V Rouse

James Douglas Beasom

Jack H Linn

Dustin Alexander Woodbury

Jose Avelino Delgado

Patrick Anthony Begley

Jeanne Marie McNamara

Taewon Jung

Christopher K Davis

Thomas L Crandell

Michael Sean Carmody

Michael D Church

Leonel Ernesto Enriquez

John W Butler

Lawrence Pearce

Joseph A Czagas

Hugh C Nicolay

Chris A McCarty

Joseph S Raby

Charles Messmer

A low temperature coefficient resistor(TCRL) has some unrepaired ion implant damage. The damaged portion raises the resistance and renders the resistor less sensitive to operating temperature fluctuations. A polysilicon thin film low temperature coefficient resistor and a method for the resistor's fabrication overcomes the coefficient of resistance problem of the prior art, while at the same time eliminating steps from the BiCMOS fabrication process, optimizing bipolar design tradeoffs, and improving passive device isolation. A low temperature coefficient of resistance resistor (TCRL) is formed on a layer of insulation, typically silicon dioxide or silicon nitride, the layer comprising polysilicon having a relatively high concentration of dopants of one or more species. An annealing process is used for the implanted resistor which is shorter than that for typical prior art implanted resistors, leaving some intentional unannealed damage in the resistor. The planned damage gives the TCRL a higher resistance without increasing its temperature coefficient. A process for fabrication of the resistor is used which combines separate spacer oxide depositions, provides buried layers having different diffusion coefficients, incorporates dual dielectric trench sidewalls that double as a polish stop, supplies a spacer structure that controls precisely the emitter-base dimension, and integrates bipolar and CMOS devices with negligible compromise to the features of either type.

BICMOS process with low temperature coefficient resistor (TCRL)

A low temperature coefficient resistor (TCRL) has some unrepaired ion implant damage. The damaged portion raises the resistance and renders the resistor less sensitive to operating temperature fluctuations A polysilicon thin film low temperature coefficient resistor and a method for the resistor's fabrication overcomes the coefficient of resistance problem of the prior art, while at the same time eliminating steps from the BiCMOS fabrication process, optimizing bipolar design tradeoffs, and improving passive device isolation. A low temperature coefficient of resistance resistor (TCRL) is formed on a layer of insulation, typically silicon dioxide or silicon nitride, the layer comprising polysilicon having a relatively high concentration of dopants of one or more species. An annealing process is used for the implanted resistor which is shorter than that for typical prior art implanted resistors, leaving some intentional unannealed damage in the resistor. The planned damage gives the TCRL a higher resistance without increasing its temperature coefficient. A process for fabrication of the resistor is used which combines separate spacer oxide depositions, provides buried layers having different diffusion coefficients, incorporates dual dielectric trench sidewalls that double as a polish stop, supplies a spacer structure that controls precisely the emitter-base dimension, and integrates bipolar and CMOS devices with negligible compromise to the features of either type.

BiCMOS process with low temperature coefficient resistor (TCRL)

A bonded wafer has a device substrate with isolation trenches defining device regions Oxide dogbone structures are removed before filling trenches . Voids in the trenches are spaced from the top of the trenches. The trenches are covered with an oxide layer and filled with polysilicon A LOCOS mask structure comprising a layer of CVD pad oxide and silicon nitride cover the trenches and the adjacent device substrate regions.

Wafer trench article and process

A first thin film resistor formed by direct etch or lift off on a first dielectric layer that covers an integrated circuit in a substrate. A second thin film resistor comprised of a different material than the first resistor, formed by direct etch or lift off on the first dielectric layer or on a second dielectric layer over the first dielectric layer. The first and second thin film resistors are interconnected with another electronic device such as other resistors or the integrated circuit.

Co-patterning thin-film resistors of different compositions with a conductive hard mask and method for same

A bonded wafer has a device substrate with isolation trenches defining device regions Oxide dogbone structures are removed before filling trenches Voids in the trenches are spaced from the top of the trenches. The trenches are covered with an oxide layer and filled with polysilicon A LOCOS mask structure comprising a layer of CVD pad oxide and silicon nitride cover the trenches and the adjacent device substrate regions.

FIG. 5b shows a first thin film resistor 14 formed by direct etching or lift off on a first dielectric layer 12 that covers an integrated circuit (not shown) in a silicon substrate 10. A patterned layer of photoresist covers a portion of the second thin film resistor material 30. The second thin film resistor material 30 is different from the first thin film resistor material 14. The exposed portion of the second thin film resistor material 30 is removed to leave first and second thin film resistors on the first dielectric layer 12.

Integrated circuit with thin film resistors and a method for

A bonded wafer 100 has a device substrate 16 with isolation trenches 30 defining device regions 18. Oxide dogbone structures are removed before filling trenches 30. Voids 36 in the trenches are spaced from the top of the trenches. The trenches are covered with an oxide layer 30 and filled with polysilicon 34. A LOCOS mask structure comprising a layer of CVD pad oxide and silicon nitride 50 cover the trenches and the adjacent device substrate regions.

Process of forming trench isolation device

A fabrication process for dielectrically isolated high frequency complementary analog bipolar and CMOS transistors. Polysilicon extrinsic bases, polysilicon emitters with sidewall spacers formed after intrinsic base formation provides high current gain, large emitter-to-base breakdown voltage, large Early voltage, and high cutoff frequency.

High frequency analog transistors, method of fabrication and circuit

High frequency analog transistors method of fabrication and circuit

A bonded wafer with a bond junction having low resistivity due to the low level of oxides at the bond junction. A plasma that removes native oxide layers from wafers is exposed to the wafers. The plasma forms a hydrophobic polymer seal on the wafers, inhibiting subsequent native oxide growth upon exposure to air. The polymer seal on the wafers to be bonded are pressed together and the wafers are annealed to form the bonded wafer in a non-oxidizing ambient. The bond junction formed is primarily silicon to silicon and silicon to carbon bonds.

Bonded wafer

A method of fabricating a vertical conductive region in a semiconductor device in which plural epitaxial layers are successively grown on a substrate and a dopant is implanted into each epitaxial layer before growing the next layer. A fast vertical transistor operable in the GHz range and at high voltage (e.g., more than about 10 volts) is fabricated by growing plural epitaxial layers, each with a thickness less than about 2.5 microns until the desired height of the vertical conductive region is reached. Sections of the transistor's collector and an adjacent sinker are implanted through each epitaxial layer before the next layer is grown. Annealing after ion implant joins the sinker and collector sections in each layer with the corresponding sinker and collector sections in adjacent layers to form unitary structures in the transistor. Each layer is thin enough for the dopant to penetrate to the bottom of the layer using conventional implant energy. The manufacturing process does not limit the height of the sinker or collector.

Method of forming P-type islands over P-type buried layer

Bonded wafer and method of fabrication thereof

Recessed isolation oxide is deposited in shallow trenches simultaneoulsy with oxide deposition in deep isolation trenches. A single planarization of both trench fillings provides efficient recessed isolation oxide without bird's beak or bird's head problems of LOCOS isolation oxide. Self-aligned trench filling by successive conformal depositions of oxide and polysilicon followed by planarization to remove polysilicon away from the trenches. The the remaining polysilicon may be used as an oxide etch mask to remove all of the oxide except in the trenches.

Method for forming recessed oxide isolation containing deep and shallow

Methods of forming a carbon containing, minority carrier barrier layer on the surface of a semiconductor, which methods may be used to form barriers between the emitter of a single crystal transistor and a polysilicon layer in electrical contact therewith, and thus transistors with an emitter with enhanced efficiency.

Growing community of inventors

Melbourne, FL, United States of America

George S Bajor