International Business Machines Corporation

Other

George Russell Zettles, Iv

Layne A Berge

Wesley David Martin

Benjamin A Fox

Daniel Ramirez

Jarrett Betke

Timothy Lindquist

Jeremy T Ekman

Karl Robert Erickson

George Francis Paulik

Timothy Clyde Buchholtz

Phillip V Mann

Mark James Jeanson

Kent Harold Haselhorst

Trevor Joseph Timpane

David W Siljenberg

Ray Clement Laning

Jordan Ross Keuseman

Donald J Ziebarth

Brandon R Christenson

Austin Carter

Sierra Spring

Matthew Stephen Doyle

Gerald Keith Bartley

Paul E Schardt

Sudipto Chakraborty

Paul Eric Dahlen

Kevin O'Connell

Christopher Lee Tuma

Matthew A Walther

Jonathan Michael Allen

Richard Boyd Ericson

Pat Rosno

Richard Holmquist

Kevin Daniel Escobar

A cable connector for counting a number of plug-in events and preventing further plug in attempts after a threshold number of plug-in events have occurred. An inner sleeve is located inside an outer sleeve, and is designed to move relative to the outer sleeve. The inner sleeve further includes a tab on an outer surface of the inner sleeve. A gear wheel is located inside the outer sleeve and perpendicular to the inner sleeve and has a number of gear teeth. A toggle plug counter rotates the gear wheel one tooth in response to a plug-in action of the cable counter. When the gear wheel rotates to a point where the tab aligns with a notch in the gear wheel an inner spring at the opposite end of the inner sleeve causes the inner sleeve to move through the gear wheel such that further plugging action becomes difficult.

Plug count limiter for cables

Method, apparatus and computer program product for spur detection in a sampled waveform in a mixed analog/digital system using the magnitude of the frequency response comprising acquiring a sample waveform including a set of discrete uniformly spaced samples from a target system, wherein the sample waveform is a time domain vector; applying FFT transforming the time domain vector into the frequency domain; analyzing the frequency domain response including calculating the magnitude response; and determining whether the sample waveform has spurs including comparing the magnitude response to an average noise floor threshold including determining that the magnitude response having an average noise floor value above the average noise floor threshold has one or more spurs and determining that the magnitude response having an average noise floor value below the average noise floor threshold has no spurs, wherein a spur indicates unaligned data having a delayed bit flip.

Spur detection in a sampled waveform in a mixed analog/digital system using the magnitude of the frequency response

Systems for optimizing mounting points for coaxial RF connectors, including a printed circuit board (PCB) comprising a coaxial radio frequency (RF) connector; a faceplate comprising an opening adapted to receive the coaxial RF connector; and a bushing positioned within the opening, wherein the coaxial RF connector is positioned within the bushing.

Optimizing mounting points for coaxial RF connectors

An electronic component system includes a chassis that includes a body, an electrically isolated portion, and an insulator disposed between the electrically isolated portion and the body, wherein the insulator is comprised of a first electrically insulating material. The electronic component system further includes a first electronic component mounted to the electrically isolated portion, and a second electronic component mounted to the body and electrically connected to the first electronic component.

Isolated component mounting scheme

Techniques facilitating write-only device state inferences. In one example, a system can comprise a processor that executes computer executable components stored in memory. The computer executable components comprise: a monitor component; and a state component. The monitor component can compare a property of a feedback signal output by a write-only device with a reference signal. The state component can determine a state of the write-only device based on a comparison between the property and the reference signal.

Inferring the state of a write-only device by mapping control register values and feedback signal values

One or more systems, devices, and/or methods provided herein relate to a process for in-process radio frequency (RF) signal quality analysis and amplitude adjustment of one or more RF devices. In one or more embodiments, the RF device can comprise a portion of a quantum computing system, such as of readout electronics thereof, and thus amplitude adjustment can be at a waveform generator that generates pulses to affect one or more qubits of a quantum logic circuit of the quantum computing system. Generally, an electronic device can comprise an RF tap connected to an RF signal component of a first RF signal chain, and an analysis component connected to the RF tap, the analysis component configured to convert an RF signal from the RF signal component and to compare a conversion result thereof to an expected power output that is based on historical data for a second RF signal chain.

Radio frequency signal integrity verification

Systems, devices, computer-implemented methods, and/or computer program products that facilitate low power, wideband multitone generation. In one example, a multitone generator device can comprise a controller operatively coupled to first and second digital-to-analog converters (DACs). The controller can apply different delays of a sampling signal to the first and second DACs to facilitate sideband suppression of signals output by the first and second DACs. One aspect of such a multitone generator device is that the multitone generator device can facilitate low power, wideband multitone generation.

Low power wideband multitone generator

An apparatus includes a sampling circuit, a sense circuit, and a tuning circuit. The sampling circuit samples an input signal according to a sampling clock signal to produce a sampled signal. The sense circuit determines a scaling factor based on a distortion in the sampled signal caused by the sampling clock signal. The tuning circuit generates an offset signal based on the sampling clock signal and the scaling factor. The offset signal reduces the distortion in the sampled signal caused by the sampling clock signal.

Distortion reduction circuit

A method for providing a computer system including: a trivial file transfer protocol (TFTP) server computer, a system management controller computer and a set of subnet(s) including a first subnet, with each subnet of the set of subnet(s) including a primary computer and a plurality of host computers that respectively include a field programmable gate array (FPGA) with programmable blocks, polling, by the system management controller, each computer of the first subnet to determine that all of the computers of the first subnet are ready to receive a broadcast of an FPGA image, instructing the TFTP server computer to send the FPGA image to all of the machines of the first subnet; and sending, by the TFTP server computer and to all of the computers of the first subnet, the FPGA image.

TFTP (trivial file transfer protocol) broadcast controller

Embodiments herein discuss tuning a testing apparatus to better match the input response of a target system in which a cable will be used. For example, conductors in the cable may have a different skew depending on the system in which they are used. The testing apparatus may be tuned using frequency information regarding the type of signals that will be driven on the cable when installed in the target system. In one embodiment, the testing apparatus adjusts a testing cycle refresh rate for generating a testing signal which changes the frequency content of the testing signal. Using the adjusted testing cycle refresh rate results in the driver outputting a testing signal that better reflects the actual signals that will be transmitted on the cable in the target system.

Tuning a testing apparatus for measuring skew

Hardware assisted high speed serial (HSS) transceiver testing including receiving, by a link layer hardware state machine on a HSS transmitting device, an instruction to generate a test pattern, wherein the test pattern comprises a sequence of data units; loading, by the link layer hardware state machine, each unique data unit into embedded random access memory (RAM); generating, by the link layer hardware state machine, the test pattern comprising the sequence of data units using the unique data units stored in the embedded RAM, wherein at least one of the unique data units is repeated in the sequence of data units of the test pattern; and sending, by the link layer hardware state machine, the generated test pattern to an input of a HSS transceiver.

Hardware assisted high speed serial transceiver testing

Hardware error detection on a high-speed serial (HSS) connection including tracking, by a hardware state machine on a HSS receiver, errors in a data stream, wherein tracking, by the hardware state machine, the errors in the data stream comprises, for each sample of incoming data: inspecting, by the hardware state machine, a detected error indicator in a test control register to determine whether an error has been detected in the sample; incrementing, by the hardware state machine, an error count in a hardware error counter if the test control register indicates an error has been detected in the sample; clearing, by the hardware state machine, the detected error indicator if the test control register indicates an error has been detected in the sample; and incrementing, by the hardware state machine, a sample count in a sample count register.

Hardware error detection on a high-speed serial connection

The embodiments of the present disclosure identify a target chip from among multiple chips coupled to a shared bus and customize an optimization parameter for the particular chip. Stated differently, in a communication system where only one chip (or a subset of chips) on a shared bus is the intended target, the system can customize an optimization parameter for the specific location of the target chip on the bus. As new data is received that is intended for a different chip&#x2014;i.e., the target chip changes&#x2014;the system can dynamically change the parameter based on the location of the new target chip on the bus.

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Rochester, MN, United States of America

George Russell Zettles, Iv