Nxp USA, Inc.

Arizona State University

George Rogers Kunnen

Brandt Braswell

Mark Lancaster

David R Allee

Srikanth Jagannathan

Christopher James Micielli

Edward John Bawolek

Carl Culshaw

Jitendran Muthuswamy

Joseph T Smith

Michael Goryll

Jennifer Blain Christen

Barry O'Brien

Yong-Kyun Lee

Edward H Lee

An A/D converter includes multiple bin comparators that compare an analog voltage to corresponding bin threshold voltages to provide output signals for providing corresponding comparison results. Some of the comparators includes enable inputs that selectively enable the output signal of the bin comparator to provide the corresponding comparison result based on a corresponding comparison result from at least one other bin comparator. The A/D convertor includes an encoder that utilizes the output signals to provide encoded bit values of the digital output. The A/D converter includes a bin selection circuit that utilizes the output signals to select a voltage level based on the output signals and provides the selected voltage level to a next stage of the A/D convertor. The next stage uses the selected voltage level and the analog voltage to provide at least one lessor bit of the digital output.

Analog to digital converter

Time-interleaved analog-to-digital converters (ADCs) and related methods are disclosed that are based upon multiplying digital-to-analog converters (MDACs). For one ADC embodiment, a sample-and-hold circuit receives an input signal and outputs a voltage that represents the input signal. An MDAC receives the voltage, outputs an N-bit digital value, and outputs a current that represents the voltage. A phased current generator receives the current and outputs time-interleaved currents that are based upon the current. An array of sub-ADCs receive the time-interleaved currents, and each sub-ADC outputs a digital value. The digital values from the array of sub-ADCs are then combined and to output an M-bit digital value. The N-bit digital value and the M-bit digital value provide a digital conversion output for the ADC.

MDAC based time-interleaved analog-to-digital converters and related methods

A circuit includes a first external terminal, a first lower resolution analog-to-digital converter (LRADC) coupled to the external terminal and configured to perform a first conversion of an analog signal received at the external terminal to a digital value, and a higher resolution analog-to-digital converter (HRADC). The HRADC is configured to selectively receive the analog signal from the first external terminal based on the digital value. When the digital value outputted by the first LRADC indicates a change in value of the received analog signal, the HRADC is provided with the analog signal and performs a second conversion of the analog signal to a second digital value. The first LRADC has a lower conversion resolution as compared to the HRADC.

Circuit with analog-to-digital converters of different conversion resolutions

Systems and methods for stimulating neural tissue are disclosed. An array of optically emissive pixels is configured to deliver light to the neural tissue of a subject. Individual pixels within the array can be addressed to selectively illuminate a portion of the neural tissue when a neurological event occurs. The system can also include an array of microelectrodes in electrical communication with the array of pixels and a power source. A biocompatible substrate can be used to support the microelectrodes pixels, and the power source. A microelectrode circuit and a pixel circuit can also be supported by the biocompatible substrate.

Integrated high-resolution untethered flexible neural implant

Current controlled multiplying digital-to-analog converters (MDACs) and related methods are disclosed for time-interleaved analog-to-digital converters (ADCs). For one embodiment, a circuit includes an MDAC having an amplifier that converts a voltage to an output current, a variable load that is dependent upon a digital value and that controls the output current from the amplifier, and an array of comparators that receive the voltage and output the digital value to the variable load. The digital value represents at least a portion of a digital conversion of the voltage. Further, the circuit can include a phased current generator that receives the output current and generates time-interleaved currents where each time-interleaved current is a sampled copy of the output current.

Current controlled MDAC for time-interleaved ADCS and related methods

Digital calibration systems and related methods are disclosed for multi-stage analog-to-digital converters (ADCs). For one embodiment, a multi-stage ADC includes an initial ADC, an additional ADC, and calibration logic. The initial ADC generates an output signal and N-bit digital values that are based upon an input signal. The additional ADC receives the output signal from the initial ADC and generates M-bit digital values that are based upon the output signal. The calibration logic receives the N-bit digital values and the M-bit digital values and generates correction values. The correction values are based upon differences between maximum values and minimum values for M-bit digital values associated with different regions determined by the N-bit digital values. Digital conversion outputs for the multi-stage ADC are provided as combinations of the N-bit digital values and the M-bit digital values corrected with the correction values.

Digital calibration systems and methods for multi-stage analog-to-digital converters

A digital to analog converter (DAC) circuit includes pulse generator circuit for generating voltage pulses having a predetermined length and shape. The voltage pulses are used to control the generation of current pulses generated by a voltage to current converter. The voltage to current converter includes a set of switchable resistors where the resistance value provided by the set is dependent upon a digital value of a digital signal. In some embodiments, the current amplitude of the current pulses is dependent upon the resistance value and is indicative of the digital value.

Digital to analog converter

Some embodiments include a system. The system includes a sensor device having a sensor element having a sensor output and an amplification element having at least one amplification stage, an amplifier input, and an amplifier output. The sensor output can be coupled to the amplifier input. Further, each amplification stage of the amplification stage(s) can have at least four thin film transistors, an input node, and an output node. Meanwhile, the sensor element can detect a physical quantity and/or an event and can provide an electric signal to the amplification element in response to detecting the physical quantity and/or the event, and the amplification element can amplify the electric signal received from the sensor element. Other embodiments of related systems and methods are also disclosed.

Thin film transistor detection systems and related methods

A multi-rate cascaded continuous-time analog-to-digital converter has a plurality of sigma-delta modulator stages and includes first and second continuous-time sigma-delta modulators, and a summation element. The first continuous-time sigma-delta modulator operates at a first sampling rate. The second continuous-time sigma-delta modulator operates at a second sampling rate higher than the first sampling rate. The second continuous-time sigma-delta modulator has a continuous-time voltage controlled oscillator (VCO) quantizer, and a feedback loop coupled between the input and the output. The second continuous-time sigma-delta modulator is cascaded with the first continuous-time sigma-delta modulator. The summation element has inputs coupled to outputs of the first and second continuous-time sigma-delta modulators.

Continuous-time cascaded sigma-delta analog-to-digital converter

The embodiments described herein provide analog-to-digital converters (ADCs) and systems and methods for calibrating ADCs, including ADCs with poorly characterized nonlinearities that cannot be effectively calibrated with traditional calibration techniques. In general, the embodiments described herein calibrate by measuring output values from an ADC with a known calibration input values being applied. The measured output values are used to determine localized polynomial interpolants. Each of the determined localized polynomial interpolants is then evaluated at an uncorrected output value, and the evaluated localized polynomial interpolants are then used to generate correction values. These correction values can then be used to calibrate the ADC during later operation. Such a calibration technique can provide effective calibration for a variety of ADCs, including ADCs that use inverter-based voltage-to-current (VI) converters and current-controlled ring oscillators.

Analog-to-digital conversion with linearity calibration

The embodiments described herein provide calibration systems and methods for mixed-signal devices. Specifically, the embodiments provide systems and methods for calibrating mixed-signal devices that can facilitate effective calibration of such mixed-signal devices, including mixed-signal devices with poorly characterized nonlinearities that cannot be effectively calibrated with traditional calibration techniques. In general, the embodiments described herein calibrate by measuring output values from a mixed-signal device with a known calibration input values being applied. The measured output values are used to determine localized polynomial interpolants. Each of the determined localized polynomial interpolants is then evaluated at an uncorrected output value, and the evaluated localized polynomial interpolants are then used to generate correction values.

System and method for linearity calibration in mixed-signal devices

Embodiments of dual stage active pixel devices are described herein. Other examples, implementations, and related methods are also disclosed herein.

Growing community of inventors

Chandler, AZ, United States of America

George Rogers Kunnen