Intel Corporation

George R Hayek

Brian K Langendorf

Gary A Solomon

James M Dodd

Aniruddha Kundu

Colyn Case

Peter D MacWilliams

Kuljit Singh Bains

Jasmin Ajanovic

Guoqing C Li

Bruce A Young

Brent S Baxter

Ali S Oztaskin

David G Carson

Kim A Meinerth

Richard Malinowski

Solomon B Trainin

Andrew F Glew

Stephen S Pawlowski

Seh Kwa

William H Wang

Sang-Hee Lee

Joseph A Bennett

Harshvardhan P Sharangpani

Brian H Kim

Darren S Crews

Radhakrishnan Venkataraman

Dmitrii A Loukianov

Nicholas D Wade

Maximino Vasquez

Todd M Witter

Norman J Rasmussen

Yaniv Frishman

Thomas Gerard Willis

Richard C Calderwood

Gideon Prat

Jesse Chin

Pat Brouillette

Sylvia Downing

Abid Asghar

Etan Shirron

Rajeev K Prasad

Vallabhajosyula Zulu Somayazulu

Joe M Nardone

An approach is provided for determining a program clock reference (PCR) value validity, for avoiding inaccurate variable delay reference (VDR) values, and for avoiding a mismatch in a data packet between a sequence number and a packet number for a wireless display extension. The approach involves determining to generate a data packet carrier having an optional PCR value, a VDR) value, and a validity indicator. The approach may further involve processing the data packet carrier to determine whether the data packet carrier has the optional PCR value. The approach may also involve causing, at least in part, a surrogate PCR value to be generated based, at least in part, on a determined absence of the optional PCR value from the data packet carrier.

Method and apparatus for low jitter clock recovery in wireless display extensions

Techniques are described to transmit commands to a display device. The commands can be transmitted in header byte fields of secondary data packets. The commands can be used to cause a target device to capture a frame, enter or exit self refresh mode, or reduce power use of a connection. In addition, a request to exit main link standby mode can cause the target enter training mode without explicit command to exit main link standby mode.

Techniques to transmit commands to a target device to reduce power consumption

In a wireless video system, the clock rate for wirelessly transmitting the video data from the transmitting device should be identical to the clock rate for receiving the video data at the receiving device. But the two devices have separate clocks, whose frequencies may drift apart over time, leading the video buffer to be over run or under run. Clock synchronizing messages to prevent this may be sent at short intervals when clock synchronization is first being acquired, and at larger intervals after clock synchronization has already been achieved and is merely being maintained.

Wireless video clock synchronization to enable power saving

A monolithic cable assembly includes a communication cable and cable connectors coupled to either end of the communication cable. The communication cable includes at least one optical communication channel. The cable connectors include a physical end connector for electrically coupling to a data device connector, optoelectronic components for converting data signals between an electrical realm and an optical realm, and a passively aligned integrated lens cover. The integrated lens cover includes at least one optical pathway for coupling optical data signals between the at least one optical communication channel and the optoelectronic components.

Monolithic active optical cable assembly for data device applications and various connector types

A computer system is disclosed with a host bridge that arbitrates access to a system resource from a CPU via a host bus and from a set of bus agents via a peripheral bus. A separate set of priority classes are provided to the CPU and to the bus agents and programmable timers are included to tune system resource allocation between the host and processor busses.

System resource arbitration mechanism for a host bridge

A high throughput memory access port is provided. The port includes features which provide higher data transfer rates between system memory and video/graphics or audio adapters than is possible using standard local bus architectures, such as PCI or ISA. The port allows memory read and write requests to be pipelined in order to hide the effects of memory access latency. In particular, the port allows bus transactions to be performed in either a non-pipelined mode, such as provided by PCI, or in a pipelined mode. In the pipelined mode, one or more additional memory access requests are permitted to be inserted between a first memory access request and its corresponding data transfer. In contrast, in the non-pipelined mode, an additional memory access request cannot be inserted between a first memory access request and its corresponding data transfer.

High-throughput interconnect having pipelined and non-pipelined bus transaction modes

A computer system having an integrated bus bridge and memory controller circuit and method for enabling access to a shared memory with high bandwidth data streaming are disclosed. The integrated bus bridge and memory controller circuit performs a series of snoop ahead transactions over a first bus during access transactions to the shared memory that originate over a second bus and thereby enables high bandwidth data streaming on the second bus. The integrated bus bridge and memory controller circuit includes a peripheral write buffer that buffers write data received over the second bus and that stores a snoop done flag for the write data that indicates whether a corresponding snoop ahead transaction for the write data is complete. The integrated bus bridge and memory controller circuit further includes a peripheral read prefetch buffer that prefetches read data during read transactions over the second bus only after a corresponding snoop ahead transaction for the read data is complete.

Integrated bus bridge and memory controller that enables data streaming

A memory controller having a data strobe that tracks the column access strobe signal in a computer system having Extended Data Out (EDO) DRAMs. The data strobe signal follows, by a predetermined delay, the column access strobe signal, and therefore any skew in the column access strobe signal is inherently included within the data strobe signal. As a result, the data can be latched out, responsive to said data strobe signal, at approximately the center of the valid window.

Method and apparatus for latching data from a memory resource at a

A method and system for enhancing graphics processing through selected placement of at least one graphics operand in main memory. The system includes a graphics controller in communication with system memory through a dedicated graphics bus such as an Accelerated Graphics Port (AGP) bus. This allows texture maps, alpha blending data and other graphics information to be contained in system memory without degradation of system performance.

System and method for placement of operands in system memory

The present invention relates to a method and apparatus for buffering data. The apparatus stores information in a buffer. When the buffer is full, overflow data is stored in an overflow memory. As data is removed from the buffer, the overflow data is transferred from overflow memory to the buffer.

Memory handling system that backfills dual-port buffer from overflow

A cache memory system having a hybrid tag architecture and a series of data lines is disclosed. The cache memory includes a cache controller and a dirty tag memory included within the cache controller. The dirty tag memory indicates the status of each data line in the cache memory. A tag memory is coupled to the cache controller and is located external to the cache controller.

Hybrid tag architecture for a cache memory

A system for detecting hazardous conditions during operation of a vehicle. In one embodiment, the system includes a plurality of sensors that monitor a plurality of conditions and transmit condition signals each representing a measure of a condition. A plurality of rate determination circuits is coupled to the sensors and continually receives the condition signals, wherein each rate determination circuit calculates rates of change for the condition, including a baseline rate of change, and outputs a potential hazard value representing a deviation of a rate of change from the baseline rate that exceeds a predetermined threshold value. An evaluation circuit receives the potential hazard value, calculates a new potential hazard value using the potential hazard value and a rate of change for at least one associated condition and determines whether an actual hazard exists by comparing the new potential hazard value with a stored value that corresponds to the condition.

Method and apparatus for hazard detection and distraction avoidance for

Error correction circuitry attempts to detect and correct on the fly erroneous words within random access memory (RAM) within a computer system. RAM errors are scrubbed or corrected back in the memory without delaying the memory access cycle. Rather, the address of the section or row of RAM that contains the correctable error is latched for later used by an interrupt-driven firmware memory-error scrub routine. This routine reads and rewrites each word within the indicated memory section--the erroneous word is read, corrected on-the-fly as it is read, and then rewritten back into memory correctly. If the size of the memory section exceeds a predetermined threshold, then the process of reading and re-writing that section is divided into smaller sub-processes that are distributed in time using a delayed interrupt mechanism. Duration of each memory scrubbing subprocess is kept short enough that the response time of the computer system is not impaired with the housekeeping task of scrubbing RAM memory errors. System management interrupts and firmware may be used to implement the memory-error scrub routine, which makes it independent of and transparent to the various operating systems that may be run on the computer system.

Time-distributed ECC scrubbing to correct memory errors

A method for converting signals from one arbitration and management protocol to another. The conversion is performed by at least three state machines. The conversion circuit converts a set of signals on the first bus to a bus request signal on the second bus. The conversion circuit also converts a signal from the second bus and a set of signals on the first bus to bus grant and memory acknowledge signals on the first bus.

Method and apparatus for converting a five wire arbitration/buffer

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Cameron Park, CA, United States of America

George R Hayek